102b5d2edSShaohui Xie /* 202b5d2edSShaohui Xie * Copyright 2015 Freescale Semiconductor, Inc. 302b5d2edSShaohui Xie * 402b5d2edSShaohui Xie * SPDX-License-Identifier: GPL-2.0+ 502b5d2edSShaohui Xie */ 602b5d2edSShaohui Xie 702b5d2edSShaohui Xie #include <common.h> 802b5d2edSShaohui Xie #include <i2c.h> 902b5d2edSShaohui Xie #include <fdt_support.h> 1002b5d2edSShaohui Xie #include <asm/io.h> 1102b5d2edSShaohui Xie #include <asm/arch/clock.h> 1202b5d2edSShaohui Xie #include <asm/arch/fsl_serdes.h> 1302b5d2edSShaohui Xie #include <asm/arch/fdt.h> 1402b5d2edSShaohui Xie #include <asm/arch/soc.h> 1502b5d2edSShaohui Xie #include <ahci.h> 1602b5d2edSShaohui Xie #include <hwconfig.h> 1702b5d2edSShaohui Xie #include <mmc.h> 1802b5d2edSShaohui Xie #include <scsi.h> 1902b5d2edSShaohui Xie #include <fm_eth.h> 2002b5d2edSShaohui Xie #include <fsl_csu.h> 2102b5d2edSShaohui Xie #include <fsl_esdhc.h> 2202b5d2edSShaohui Xie #include <fsl_ifc.h> 2302b5d2edSShaohui Xie #include <spl.h> 2402b5d2edSShaohui Xie 2502b5d2edSShaohui Xie #include "../common/qixis.h" 2602b5d2edSShaohui Xie #include "ls1043aqds_qixis.h" 2702b5d2edSShaohui Xie 2802b5d2edSShaohui Xie DECLARE_GLOBAL_DATA_PTR; 2902b5d2edSShaohui Xie 3002b5d2edSShaohui Xie enum { 3102b5d2edSShaohui Xie MUX_TYPE_GPIO, 3202b5d2edSShaohui Xie }; 3302b5d2edSShaohui Xie 3402b5d2edSShaohui Xie /* LS1043AQDS serdes mux */ 3502b5d2edSShaohui Xie #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ 3602b5d2edSShaohui Xie #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ 3702b5d2edSShaohui Xie #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ 3802b5d2edSShaohui Xie #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ 3902b5d2edSShaohui Xie #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ 4002b5d2edSShaohui Xie #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ 4102b5d2edSShaohui Xie #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ 4202b5d2edSShaohui Xie #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ 438c35cc3bSShaohui Xie #define CFG_UART_MUX_MASK 0x6 448c35cc3bSShaohui Xie #define CFG_UART_MUX_SHIFT 1 458c35cc3bSShaohui Xie #define CFG_LPUART_EN 0x1 4602b5d2edSShaohui Xie 4702b5d2edSShaohui Xie int checkboard(void) 4802b5d2edSShaohui Xie { 4902b5d2edSShaohui Xie char buf[64]; 50*b0f20cafSQianyu Gong #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 5102b5d2edSShaohui Xie u8 sw; 5202b5d2edSShaohui Xie #endif 5302b5d2edSShaohui Xie 5402b5d2edSShaohui Xie puts("Board: LS1043AQDS, boot from "); 5502b5d2edSShaohui Xie 5602b5d2edSShaohui Xie #ifdef CONFIG_SD_BOOT 5702b5d2edSShaohui Xie puts("SD\n"); 58*b0f20cafSQianyu Gong #elif defined(CONFIG_QSPI_BOOT) 59*b0f20cafSQianyu Gong puts("QSPI\n"); 6002b5d2edSShaohui Xie #else 6102b5d2edSShaohui Xie sw = QIXIS_READ(brdcfg[0]); 6202b5d2edSShaohui Xie sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 6302b5d2edSShaohui Xie 6402b5d2edSShaohui Xie if (sw < 0x8) 6502b5d2edSShaohui Xie printf("vBank: %d\n", sw); 6602b5d2edSShaohui Xie else if (sw == 0x8) 6702b5d2edSShaohui Xie puts("PromJet\n"); 6802b5d2edSShaohui Xie else if (sw == 0x9) 6902b5d2edSShaohui Xie puts("NAND\n"); 7002b5d2edSShaohui Xie else if (sw == 0x15) 7102b5d2edSShaohui Xie printf("IFCCard\n"); 7202b5d2edSShaohui Xie else 7302b5d2edSShaohui Xie printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 7402b5d2edSShaohui Xie #endif 7502b5d2edSShaohui Xie 7602b5d2edSShaohui Xie printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 7702b5d2edSShaohui Xie QIXIS_READ(id), QIXIS_READ(arch)); 7802b5d2edSShaohui Xie 7902b5d2edSShaohui Xie printf("FPGA: v%d (%s), build %d\n", 8002b5d2edSShaohui Xie (int)QIXIS_READ(scver), qixis_read_tag(buf), 8102b5d2edSShaohui Xie (int)qixis_read_minor()); 8202b5d2edSShaohui Xie 8302b5d2edSShaohui Xie return 0; 8402b5d2edSShaohui Xie } 8502b5d2edSShaohui Xie 8602b5d2edSShaohui Xie bool if_board_diff_clk(void) 8702b5d2edSShaohui Xie { 8802b5d2edSShaohui Xie u8 diff_conf = QIXIS_READ(brdcfg[11]); 8902b5d2edSShaohui Xie 9002b5d2edSShaohui Xie return diff_conf & 0x40; 9102b5d2edSShaohui Xie } 9202b5d2edSShaohui Xie 9302b5d2edSShaohui Xie unsigned long get_board_sys_clk(void) 9402b5d2edSShaohui Xie { 9502b5d2edSShaohui Xie u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 9602b5d2edSShaohui Xie 9702b5d2edSShaohui Xie switch (sysclk_conf & 0x0f) { 9802b5d2edSShaohui Xie case QIXIS_SYSCLK_64: 9902b5d2edSShaohui Xie return 64000000; 10002b5d2edSShaohui Xie case QIXIS_SYSCLK_83: 10102b5d2edSShaohui Xie return 83333333; 10202b5d2edSShaohui Xie case QIXIS_SYSCLK_100: 10302b5d2edSShaohui Xie return 100000000; 10402b5d2edSShaohui Xie case QIXIS_SYSCLK_125: 10502b5d2edSShaohui Xie return 125000000; 10602b5d2edSShaohui Xie case QIXIS_SYSCLK_133: 10702b5d2edSShaohui Xie return 133333333; 10802b5d2edSShaohui Xie case QIXIS_SYSCLK_150: 10902b5d2edSShaohui Xie return 150000000; 11002b5d2edSShaohui Xie case QIXIS_SYSCLK_160: 11102b5d2edSShaohui Xie return 160000000; 11202b5d2edSShaohui Xie case QIXIS_SYSCLK_166: 11302b5d2edSShaohui Xie return 166666666; 11402b5d2edSShaohui Xie } 11502b5d2edSShaohui Xie 11602b5d2edSShaohui Xie return 66666666; 11702b5d2edSShaohui Xie } 11802b5d2edSShaohui Xie 11902b5d2edSShaohui Xie unsigned long get_board_ddr_clk(void) 12002b5d2edSShaohui Xie { 12102b5d2edSShaohui Xie u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 12202b5d2edSShaohui Xie 12302b5d2edSShaohui Xie if (if_board_diff_clk()) 12402b5d2edSShaohui Xie return get_board_sys_clk(); 12502b5d2edSShaohui Xie switch ((ddrclk_conf & 0x30) >> 4) { 12602b5d2edSShaohui Xie case QIXIS_DDRCLK_100: 12702b5d2edSShaohui Xie return 100000000; 12802b5d2edSShaohui Xie case QIXIS_DDRCLK_125: 12902b5d2edSShaohui Xie return 125000000; 13002b5d2edSShaohui Xie case QIXIS_DDRCLK_133: 13102b5d2edSShaohui Xie return 133333333; 13202b5d2edSShaohui Xie } 13302b5d2edSShaohui Xie 13402b5d2edSShaohui Xie return 66666666; 13502b5d2edSShaohui Xie } 13602b5d2edSShaohui Xie 13702b5d2edSShaohui Xie int select_i2c_ch_pca9547(u8 ch) 13802b5d2edSShaohui Xie { 13902b5d2edSShaohui Xie int ret; 14002b5d2edSShaohui Xie 14102b5d2edSShaohui Xie ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 14202b5d2edSShaohui Xie if (ret) { 14302b5d2edSShaohui Xie puts("PCA: failed to select proper channel\n"); 14402b5d2edSShaohui Xie return ret; 14502b5d2edSShaohui Xie } 14602b5d2edSShaohui Xie 14702b5d2edSShaohui Xie return 0; 14802b5d2edSShaohui Xie } 14902b5d2edSShaohui Xie 15002b5d2edSShaohui Xie int dram_init(void) 15102b5d2edSShaohui Xie { 15202b5d2edSShaohui Xie /* 15302b5d2edSShaohui Xie * When resuming from deep sleep, the I2C channel may not be 15402b5d2edSShaohui Xie * in the default channel. So, switch to the default channel 15502b5d2edSShaohui Xie * before accessing DDR SPD. 15602b5d2edSShaohui Xie */ 15702b5d2edSShaohui Xie select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 15802b5d2edSShaohui Xie gd->ram_size = initdram(0); 15902b5d2edSShaohui Xie 16002b5d2edSShaohui Xie return 0; 16102b5d2edSShaohui Xie } 16202b5d2edSShaohui Xie 16302b5d2edSShaohui Xie int i2c_multiplexer_select_vid_channel(u8 channel) 16402b5d2edSShaohui Xie { 16502b5d2edSShaohui Xie return select_i2c_ch_pca9547(channel); 16602b5d2edSShaohui Xie } 16702b5d2edSShaohui Xie 16802b5d2edSShaohui Xie void board_retimer_init(void) 16902b5d2edSShaohui Xie { 17002b5d2edSShaohui Xie u8 reg; 17102b5d2edSShaohui Xie 17202b5d2edSShaohui Xie /* Retimer is connected to I2C1_CH7_CH5 */ 17302b5d2edSShaohui Xie reg = I2C_MUX_CH7; 17402b5d2edSShaohui Xie i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); 17502b5d2edSShaohui Xie reg = I2C_MUX_CH5; 17602b5d2edSShaohui Xie i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 17702b5d2edSShaohui Xie 17802b5d2edSShaohui Xie /* Access to Control/Shared register */ 17902b5d2edSShaohui Xie reg = 0x0; 18002b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 18102b5d2edSShaohui Xie 18202b5d2edSShaohui Xie /* Read device revision and ID */ 18302b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 18402b5d2edSShaohui Xie debug("Retimer version id = 0x%x\n", reg); 18502b5d2edSShaohui Xie 18602b5d2edSShaohui Xie /* Enable Broadcast. All writes target all channel register sets */ 18702b5d2edSShaohui Xie reg = 0x0c; 18802b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 18902b5d2edSShaohui Xie 19002b5d2edSShaohui Xie /* Reset Channel Registers */ 19102b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 19202b5d2edSShaohui Xie reg |= 0x4; 19302b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 19402b5d2edSShaohui Xie 19502b5d2edSShaohui Xie /* Enable override divider select and Enable Override Output Mux */ 19602b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 19702b5d2edSShaohui Xie reg |= 0x24; 19802b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 19902b5d2edSShaohui Xie 20002b5d2edSShaohui Xie /* Select VCO Divider to full rate (000) */ 20102b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 20202b5d2edSShaohui Xie reg &= 0x8f; 20302b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 20402b5d2edSShaohui Xie 20502b5d2edSShaohui Xie /* Selects active PFD MUX Input as Re-timed Data (001) */ 20602b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 20702b5d2edSShaohui Xie reg &= 0x3f; 20802b5d2edSShaohui Xie reg |= 0x20; 20902b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 21002b5d2edSShaohui Xie 21102b5d2edSShaohui Xie /* Set data rate as 10.3125 Gbps */ 21202b5d2edSShaohui Xie reg = 0x0; 21302b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 21402b5d2edSShaohui Xie reg = 0xb2; 21502b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 21602b5d2edSShaohui Xie reg = 0x90; 21702b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 21802b5d2edSShaohui Xie reg = 0xb3; 21902b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 22002b5d2edSShaohui Xie reg = 0xcd; 22102b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 22202b5d2edSShaohui Xie } 22302b5d2edSShaohui Xie 22402b5d2edSShaohui Xie int board_early_init_f(void) 22502b5d2edSShaohui Xie { 2268c35cc3bSShaohui Xie #ifdef CONFIG_LPUART 2278c35cc3bSShaohui Xie u8 uart; 2288c35cc3bSShaohui Xie #endif 22902b5d2edSShaohui Xie fsl_lsch2_early_init_f(); 2308c35cc3bSShaohui Xie #ifdef CONFIG_LPUART 2318c35cc3bSShaohui Xie /* We use lpuart0 as system console */ 2328c35cc3bSShaohui Xie uart = QIXIS_READ(brdcfg[14]); 2338c35cc3bSShaohui Xie uart &= ~CFG_UART_MUX_MASK; 2348c35cc3bSShaohui Xie uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; 2358c35cc3bSShaohui Xie QIXIS_WRITE(brdcfg[14], uart); 2368c35cc3bSShaohui Xie #endif 23702b5d2edSShaohui Xie 23802b5d2edSShaohui Xie return 0; 23902b5d2edSShaohui Xie } 24002b5d2edSShaohui Xie 24102b5d2edSShaohui Xie #ifdef CONFIG_FSL_DEEP_SLEEP 24202b5d2edSShaohui Xie /* determine if it is a warm boot */ 24302b5d2edSShaohui Xie bool is_warm_boot(void) 24402b5d2edSShaohui Xie { 24502b5d2edSShaohui Xie #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 24602b5d2edSShaohui Xie struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 24702b5d2edSShaohui Xie 24802b5d2edSShaohui Xie if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 24902b5d2edSShaohui Xie return 1; 25002b5d2edSShaohui Xie 25102b5d2edSShaohui Xie return 0; 25202b5d2edSShaohui Xie } 25302b5d2edSShaohui Xie #endif 25402b5d2edSShaohui Xie 25502b5d2edSShaohui Xie int config_board_mux(int ctrl_type) 25602b5d2edSShaohui Xie { 25702b5d2edSShaohui Xie u8 reg14; 25802b5d2edSShaohui Xie 25902b5d2edSShaohui Xie reg14 = QIXIS_READ(brdcfg[14]); 26002b5d2edSShaohui Xie 26102b5d2edSShaohui Xie switch (ctrl_type) { 26202b5d2edSShaohui Xie case MUX_TYPE_GPIO: 26302b5d2edSShaohui Xie reg14 = (reg14 & (~0x30)) | 0x20; 26402b5d2edSShaohui Xie break; 26502b5d2edSShaohui Xie default: 26602b5d2edSShaohui Xie puts("Unsupported mux interface type\n"); 26702b5d2edSShaohui Xie return -1; 26802b5d2edSShaohui Xie } 26902b5d2edSShaohui Xie 27002b5d2edSShaohui Xie QIXIS_WRITE(brdcfg[14], reg14); 27102b5d2edSShaohui Xie 27202b5d2edSShaohui Xie return 0; 27302b5d2edSShaohui Xie } 27402b5d2edSShaohui Xie 27502b5d2edSShaohui Xie int config_serdes_mux(void) 27602b5d2edSShaohui Xie { 27702b5d2edSShaohui Xie return 0; 27802b5d2edSShaohui Xie } 27902b5d2edSShaohui Xie 28002b5d2edSShaohui Xie 28102b5d2edSShaohui Xie #ifdef CONFIG_MISC_INIT_R 28202b5d2edSShaohui Xie int misc_init_r(void) 28302b5d2edSShaohui Xie { 28402b5d2edSShaohui Xie if (hwconfig("gpio")) 28502b5d2edSShaohui Xie config_board_mux(MUX_TYPE_GPIO); 28602b5d2edSShaohui Xie 28702b5d2edSShaohui Xie return 0; 28802b5d2edSShaohui Xie } 28902b5d2edSShaohui Xie #endif 29002b5d2edSShaohui Xie 29102b5d2edSShaohui Xie int board_init(void) 29202b5d2edSShaohui Xie { 29302b5d2edSShaohui Xie struct ccsr_cci400 *cci = (struct ccsr_cci400 *) 29402b5d2edSShaohui Xie CONFIG_SYS_CCI400_ADDR; 29502b5d2edSShaohui Xie 29602b5d2edSShaohui Xie /* Set CCI-400 control override register to enable barrier 29702b5d2edSShaohui Xie * transaction */ 29802b5d2edSShaohui Xie out_le32(&cci->ctrl_ord, 29902b5d2edSShaohui Xie CCI400_CTRLORD_EN_BARRIER); 30002b5d2edSShaohui Xie 30102b5d2edSShaohui Xie select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 30202b5d2edSShaohui Xie board_retimer_init(); 30302b5d2edSShaohui Xie 30402b5d2edSShaohui Xie #ifdef CONFIG_SYS_FSL_SERDES 30502b5d2edSShaohui Xie config_serdes_mux(); 30602b5d2edSShaohui Xie #endif 30702b5d2edSShaohui Xie 30802b5d2edSShaohui Xie #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 30902b5d2edSShaohui Xie enable_layerscape_ns_access(); 31002b5d2edSShaohui Xie #endif 31102b5d2edSShaohui Xie 31202b5d2edSShaohui Xie #ifdef CONFIG_ENV_IS_NOWHERE 31302b5d2edSShaohui Xie gd->env_addr = (ulong)&default_environment[0]; 31402b5d2edSShaohui Xie #endif 31502b5d2edSShaohui Xie return 0; 31602b5d2edSShaohui Xie } 31702b5d2edSShaohui Xie 31802b5d2edSShaohui Xie #ifdef CONFIG_OF_BOARD_SETUP 31902b5d2edSShaohui Xie int ft_board_setup(void *blob, bd_t *bd) 32002b5d2edSShaohui Xie { 32158e4ad1dSShaohui Xie u64 base[CONFIG_NR_DRAM_BANKS]; 32258e4ad1dSShaohui Xie u64 size[CONFIG_NR_DRAM_BANKS]; 32358e4ad1dSShaohui Xie 32458e4ad1dSShaohui Xie /* fixup DT for the two DDR banks */ 32558e4ad1dSShaohui Xie base[0] = gd->bd->bi_dram[0].start; 32658e4ad1dSShaohui Xie size[0] = gd->bd->bi_dram[0].size; 32758e4ad1dSShaohui Xie base[1] = gd->bd->bi_dram[1].start; 32858e4ad1dSShaohui Xie size[1] = gd->bd->bi_dram[1].size; 32958e4ad1dSShaohui Xie 33058e4ad1dSShaohui Xie fdt_fixup_memory_banks(blob, base, size, 2); 33102b5d2edSShaohui Xie ft_cpu_setup(blob, bd); 33202b5d2edSShaohui Xie 33302b5d2edSShaohui Xie #ifdef CONFIG_SYS_DPAA_FMAN 33402b5d2edSShaohui Xie fdt_fixup_fman_ethernet(blob); 33502b5d2edSShaohui Xie fdt_fixup_board_enet(blob); 33602b5d2edSShaohui Xie #endif 33702b5d2edSShaohui Xie return 0; 33802b5d2edSShaohui Xie } 33902b5d2edSShaohui Xie #endif 34002b5d2edSShaohui Xie 34102b5d2edSShaohui Xie u8 flash_read8(void *addr) 34202b5d2edSShaohui Xie { 34302b5d2edSShaohui Xie return __raw_readb(addr + 1); 34402b5d2edSShaohui Xie } 34502b5d2edSShaohui Xie 34602b5d2edSShaohui Xie void flash_write16(u16 val, void *addr) 34702b5d2edSShaohui Xie { 34802b5d2edSShaohui Xie u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 34902b5d2edSShaohui Xie 35002b5d2edSShaohui Xie __raw_writew(shftval, addr); 35102b5d2edSShaohui Xie } 35202b5d2edSShaohui Xie 35302b5d2edSShaohui Xie u16 flash_read16(void *addr) 35402b5d2edSShaohui Xie { 35502b5d2edSShaohui Xie u16 val = __raw_readw(addr); 35602b5d2edSShaohui Xie 35702b5d2edSShaohui Xie return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 35802b5d2edSShaohui Xie } 359