183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 202b5d2edSShaohui Xie /* 302b5d2edSShaohui Xie * Copyright 2015 Freescale Semiconductor, Inc. 402b5d2edSShaohui Xie */ 502b5d2edSShaohui Xie 602b5d2edSShaohui Xie #include <common.h> 702b5d2edSShaohui Xie #include <i2c.h> 802b5d2edSShaohui Xie #include <fdt_support.h> 93eace37eSSimon Glass #include <fsl_ddr_sdram.h> 1002b5d2edSShaohui Xie #include <asm/io.h> 1102b5d2edSShaohui Xie #include <asm/arch/clock.h> 1202b5d2edSShaohui Xie #include <asm/arch/fsl_serdes.h> 13e1b09290SHou Zhiqiang #include <asm/arch/ppa.h> 1402b5d2edSShaohui Xie #include <asm/arch/fdt.h> 154961eafcSYork Sun #include <asm/arch/mmu.h> 16*8aa6b17aSRajesh Bhagat #include <asm/arch/cpu.h> 1702b5d2edSShaohui Xie #include <asm/arch/soc.h> 18dc29a4c1SLaurentiu Tudor #include <asm/arch-fsl-layerscape/fsl_icid.h> 1902b5d2edSShaohui Xie #include <ahci.h> 2002b5d2edSShaohui Xie #include <hwconfig.h> 2102b5d2edSShaohui Xie #include <mmc.h> 2202b5d2edSShaohui Xie #include <scsi.h> 2302b5d2edSShaohui Xie #include <fm_eth.h> 2402b5d2edSShaohui Xie #include <fsl_esdhc.h> 2502b5d2edSShaohui Xie #include <fsl_ifc.h> 2602b5d2edSShaohui Xie #include <spl.h> 2702b5d2edSShaohui Xie 2802b5d2edSShaohui Xie #include "../common/qixis.h" 2902b5d2edSShaohui Xie #include "ls1043aqds_qixis.h" 3002b5d2edSShaohui Xie 3102b5d2edSShaohui Xie DECLARE_GLOBAL_DATA_PTR; 3202b5d2edSShaohui Xie 3302b5d2edSShaohui Xie enum { 3402b5d2edSShaohui Xie MUX_TYPE_GPIO, 3502b5d2edSShaohui Xie }; 3602b5d2edSShaohui Xie 3702b5d2edSShaohui Xie /* LS1043AQDS serdes mux */ 3802b5d2edSShaohui Xie #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ 3902b5d2edSShaohui Xie #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ 4002b5d2edSShaohui Xie #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ 4102b5d2edSShaohui Xie #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ 4202b5d2edSShaohui Xie #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ 4302b5d2edSShaohui Xie #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ 4402b5d2edSShaohui Xie #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ 4502b5d2edSShaohui Xie #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ 468c35cc3bSShaohui Xie #define CFG_UART_MUX_MASK 0x6 478c35cc3bSShaohui Xie #define CFG_UART_MUX_SHIFT 1 488c35cc3bSShaohui Xie #define CFG_LPUART_EN 0x1 4902b5d2edSShaohui Xie 50*8aa6b17aSRajesh Bhagat #ifdef CONFIG_TFABOOT 51*8aa6b17aSRajesh Bhagat struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 52*8aa6b17aSRajesh Bhagat { 53*8aa6b17aSRajesh Bhagat "nor0", 54*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR0_CSPR, 55*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR0_CSPR_EXT, 56*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_AMASK, 57*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_CSOR, 58*8aa6b17aSRajesh Bhagat { 59*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM0, 60*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM1, 61*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM2, 62*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM3 63*8aa6b17aSRajesh Bhagat }, 64*8aa6b17aSRajesh Bhagat 65*8aa6b17aSRajesh Bhagat }, 66*8aa6b17aSRajesh Bhagat { 67*8aa6b17aSRajesh Bhagat "nor1", 68*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR1_CSPR, 69*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR1_CSPR_EXT, 70*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_AMASK, 71*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_CSOR, 72*8aa6b17aSRajesh Bhagat { 73*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM0, 74*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM1, 75*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM2, 76*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM3 77*8aa6b17aSRajesh Bhagat }, 78*8aa6b17aSRajesh Bhagat }, 79*8aa6b17aSRajesh Bhagat { 80*8aa6b17aSRajesh Bhagat "nand", 81*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSPR, 82*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSPR_EXT, 83*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_AMASK, 84*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSOR, 85*8aa6b17aSRajesh Bhagat { 86*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM0, 87*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM1, 88*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM2, 89*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM3 90*8aa6b17aSRajesh Bhagat }, 91*8aa6b17aSRajesh Bhagat }, 92*8aa6b17aSRajesh Bhagat { 93*8aa6b17aSRajesh Bhagat "fpga", 94*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSPR, 95*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSPR_EXT, 96*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_AMASK, 97*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSOR, 98*8aa6b17aSRajesh Bhagat { 99*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM0, 100*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM1, 101*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM2, 102*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM3 103*8aa6b17aSRajesh Bhagat }, 104*8aa6b17aSRajesh Bhagat } 105*8aa6b17aSRajesh Bhagat }; 106*8aa6b17aSRajesh Bhagat 107*8aa6b17aSRajesh Bhagat struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 108*8aa6b17aSRajesh Bhagat { 109*8aa6b17aSRajesh Bhagat "nand", 110*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSPR, 111*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSPR_EXT, 112*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_AMASK, 113*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_CSOR, 114*8aa6b17aSRajesh Bhagat { 115*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM0, 116*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM1, 117*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM2, 118*8aa6b17aSRajesh Bhagat CONFIG_SYS_NAND_FTIM3 119*8aa6b17aSRajesh Bhagat }, 120*8aa6b17aSRajesh Bhagat }, 121*8aa6b17aSRajesh Bhagat { 122*8aa6b17aSRajesh Bhagat "nor0", 123*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR0_CSPR, 124*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR0_CSPR_EXT, 125*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_AMASK, 126*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_CSOR, 127*8aa6b17aSRajesh Bhagat { 128*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM0, 129*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM1, 130*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM2, 131*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM3 132*8aa6b17aSRajesh Bhagat }, 133*8aa6b17aSRajesh Bhagat }, 134*8aa6b17aSRajesh Bhagat { 135*8aa6b17aSRajesh Bhagat "nor1", 136*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR1_CSPR, 137*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR1_CSPR_EXT, 138*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_AMASK, 139*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_CSOR, 140*8aa6b17aSRajesh Bhagat { 141*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM0, 142*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM1, 143*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM2, 144*8aa6b17aSRajesh Bhagat CONFIG_SYS_NOR_FTIM3 145*8aa6b17aSRajesh Bhagat }, 146*8aa6b17aSRajesh Bhagat }, 147*8aa6b17aSRajesh Bhagat { 148*8aa6b17aSRajesh Bhagat "fpga", 149*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSPR, 150*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSPR_EXT, 151*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_AMASK, 152*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_CSOR, 153*8aa6b17aSRajesh Bhagat { 154*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM0, 155*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM1, 156*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM2, 157*8aa6b17aSRajesh Bhagat CONFIG_SYS_FPGA_FTIM3 158*8aa6b17aSRajesh Bhagat }, 159*8aa6b17aSRajesh Bhagat } 160*8aa6b17aSRajesh Bhagat }; 161*8aa6b17aSRajesh Bhagat 162*8aa6b17aSRajesh Bhagat void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) 163*8aa6b17aSRajesh Bhagat { 164*8aa6b17aSRajesh Bhagat enum boot_src src = get_boot_src(); 165*8aa6b17aSRajesh Bhagat 166*8aa6b17aSRajesh Bhagat if (src == BOOT_SOURCE_IFC_NAND) 167*8aa6b17aSRajesh Bhagat regs_info->regs = ifc_cfg_nand_boot; 168*8aa6b17aSRajesh Bhagat else 169*8aa6b17aSRajesh Bhagat regs_info->regs = ifc_cfg_nor_boot; 170*8aa6b17aSRajesh Bhagat regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; 171*8aa6b17aSRajesh Bhagat } 172*8aa6b17aSRajesh Bhagat #endif 173*8aa6b17aSRajesh Bhagat 17402b5d2edSShaohui Xie int checkboard(void) 17502b5d2edSShaohui Xie { 176*8aa6b17aSRajesh Bhagat #ifdef CONFIG_TFABOOT 177*8aa6b17aSRajesh Bhagat enum boot_src src = get_boot_src(); 178*8aa6b17aSRajesh Bhagat #endif 17902b5d2edSShaohui Xie char buf[64]; 180a2fd238eSQianyu Gong #ifndef CONFIG_SD_BOOT 18102b5d2edSShaohui Xie u8 sw; 18202b5d2edSShaohui Xie #endif 18302b5d2edSShaohui Xie 18402b5d2edSShaohui Xie puts("Board: LS1043AQDS, boot from "); 18502b5d2edSShaohui Xie 186*8aa6b17aSRajesh Bhagat #ifdef CONFIG_TFABOOT 187*8aa6b17aSRajesh Bhagat if (src == BOOT_SOURCE_SD_MMC) 188*8aa6b17aSRajesh Bhagat puts("SD\n"); 189*8aa6b17aSRajesh Bhagat else { 190*8aa6b17aSRajesh Bhagat #endif 191*8aa6b17aSRajesh Bhagat 19202b5d2edSShaohui Xie #ifdef CONFIG_SD_BOOT 19302b5d2edSShaohui Xie puts("SD\n"); 19402b5d2edSShaohui Xie #else 19502b5d2edSShaohui Xie sw = QIXIS_READ(brdcfg[0]); 19602b5d2edSShaohui Xie sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 19702b5d2edSShaohui Xie 19802b5d2edSShaohui Xie if (sw < 0x8) 19902b5d2edSShaohui Xie printf("vBank: %d\n", sw); 20002b5d2edSShaohui Xie else if (sw == 0x8) 20102b5d2edSShaohui Xie puts("PromJet\n"); 20202b5d2edSShaohui Xie else if (sw == 0x9) 20302b5d2edSShaohui Xie puts("NAND\n"); 204a2fd238eSQianyu Gong else if (sw == 0xF) 205a2fd238eSQianyu Gong printf("QSPI\n"); 20602b5d2edSShaohui Xie else 20702b5d2edSShaohui Xie printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 20802b5d2edSShaohui Xie #endif 20902b5d2edSShaohui Xie 210*8aa6b17aSRajesh Bhagat #ifdef CONFIG_TFABOOT 211*8aa6b17aSRajesh Bhagat } 212*8aa6b17aSRajesh Bhagat #endif 21302b5d2edSShaohui Xie printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 21402b5d2edSShaohui Xie QIXIS_READ(id), QIXIS_READ(arch)); 21502b5d2edSShaohui Xie 21602b5d2edSShaohui Xie printf("FPGA: v%d (%s), build %d\n", 21702b5d2edSShaohui Xie (int)QIXIS_READ(scver), qixis_read_tag(buf), 21802b5d2edSShaohui Xie (int)qixis_read_minor()); 21902b5d2edSShaohui Xie 22002b5d2edSShaohui Xie return 0; 22102b5d2edSShaohui Xie } 22202b5d2edSShaohui Xie 22302b5d2edSShaohui Xie bool if_board_diff_clk(void) 22402b5d2edSShaohui Xie { 22502b5d2edSShaohui Xie u8 diff_conf = QIXIS_READ(brdcfg[11]); 22602b5d2edSShaohui Xie 22702b5d2edSShaohui Xie return diff_conf & 0x40; 22802b5d2edSShaohui Xie } 22902b5d2edSShaohui Xie 23002b5d2edSShaohui Xie unsigned long get_board_sys_clk(void) 23102b5d2edSShaohui Xie { 23202b5d2edSShaohui Xie u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 23302b5d2edSShaohui Xie 23402b5d2edSShaohui Xie switch (sysclk_conf & 0x0f) { 23502b5d2edSShaohui Xie case QIXIS_SYSCLK_64: 23602b5d2edSShaohui Xie return 64000000; 23702b5d2edSShaohui Xie case QIXIS_SYSCLK_83: 23802b5d2edSShaohui Xie return 83333333; 23902b5d2edSShaohui Xie case QIXIS_SYSCLK_100: 24002b5d2edSShaohui Xie return 100000000; 24102b5d2edSShaohui Xie case QIXIS_SYSCLK_125: 24202b5d2edSShaohui Xie return 125000000; 24302b5d2edSShaohui Xie case QIXIS_SYSCLK_133: 24402b5d2edSShaohui Xie return 133333333; 24502b5d2edSShaohui Xie case QIXIS_SYSCLK_150: 24602b5d2edSShaohui Xie return 150000000; 24702b5d2edSShaohui Xie case QIXIS_SYSCLK_160: 24802b5d2edSShaohui Xie return 160000000; 24902b5d2edSShaohui Xie case QIXIS_SYSCLK_166: 25002b5d2edSShaohui Xie return 166666666; 25102b5d2edSShaohui Xie } 25202b5d2edSShaohui Xie 25302b5d2edSShaohui Xie return 66666666; 25402b5d2edSShaohui Xie } 25502b5d2edSShaohui Xie 25602b5d2edSShaohui Xie unsigned long get_board_ddr_clk(void) 25702b5d2edSShaohui Xie { 25802b5d2edSShaohui Xie u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 25902b5d2edSShaohui Xie 26002b5d2edSShaohui Xie if (if_board_diff_clk()) 26102b5d2edSShaohui Xie return get_board_sys_clk(); 26202b5d2edSShaohui Xie switch ((ddrclk_conf & 0x30) >> 4) { 26302b5d2edSShaohui Xie case QIXIS_DDRCLK_100: 26402b5d2edSShaohui Xie return 100000000; 26502b5d2edSShaohui Xie case QIXIS_DDRCLK_125: 26602b5d2edSShaohui Xie return 125000000; 26702b5d2edSShaohui Xie case QIXIS_DDRCLK_133: 26802b5d2edSShaohui Xie return 133333333; 26902b5d2edSShaohui Xie } 27002b5d2edSShaohui Xie 27102b5d2edSShaohui Xie return 66666666; 27202b5d2edSShaohui Xie } 27302b5d2edSShaohui Xie 27402b5d2edSShaohui Xie int select_i2c_ch_pca9547(u8 ch) 27502b5d2edSShaohui Xie { 27602b5d2edSShaohui Xie int ret; 27702b5d2edSShaohui Xie 27802b5d2edSShaohui Xie ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 27902b5d2edSShaohui Xie if (ret) { 28002b5d2edSShaohui Xie puts("PCA: failed to select proper channel\n"); 28102b5d2edSShaohui Xie return ret; 28202b5d2edSShaohui Xie } 28302b5d2edSShaohui Xie 28402b5d2edSShaohui Xie return 0; 28502b5d2edSShaohui Xie } 28602b5d2edSShaohui Xie 28702b5d2edSShaohui Xie int dram_init(void) 28802b5d2edSShaohui Xie { 28902b5d2edSShaohui Xie /* 29002b5d2edSShaohui Xie * When resuming from deep sleep, the I2C channel may not be 29102b5d2edSShaohui Xie * in the default channel. So, switch to the default channel 29202b5d2edSShaohui Xie * before accessing DDR SPD. 29302b5d2edSShaohui Xie */ 29402b5d2edSShaohui Xie select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 2953eace37eSSimon Glass fsl_initdram(); 296*8aa6b17aSRajesh Bhagat #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ 297*8aa6b17aSRajesh Bhagat defined(CONFIG_SPL_BUILD) 2984961eafcSYork Sun /* This will break-before-make MMU for DDR */ 2994961eafcSYork Sun update_early_mmu_table(); 3004961eafcSYork Sun #endif 30102b5d2edSShaohui Xie 30202b5d2edSShaohui Xie return 0; 30302b5d2edSShaohui Xie } 30402b5d2edSShaohui Xie 30502b5d2edSShaohui Xie int i2c_multiplexer_select_vid_channel(u8 channel) 30602b5d2edSShaohui Xie { 30702b5d2edSShaohui Xie return select_i2c_ch_pca9547(channel); 30802b5d2edSShaohui Xie } 30902b5d2edSShaohui Xie 31002b5d2edSShaohui Xie void board_retimer_init(void) 31102b5d2edSShaohui Xie { 31202b5d2edSShaohui Xie u8 reg; 31302b5d2edSShaohui Xie 31402b5d2edSShaohui Xie /* Retimer is connected to I2C1_CH7_CH5 */ 315ec44289dSWenbin Song select_i2c_ch_pca9547(I2C_MUX_CH7); 31602b5d2edSShaohui Xie reg = I2C_MUX_CH5; 31702b5d2edSShaohui Xie i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 31802b5d2edSShaohui Xie 31902b5d2edSShaohui Xie /* Access to Control/Shared register */ 32002b5d2edSShaohui Xie reg = 0x0; 32102b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 32202b5d2edSShaohui Xie 32302b5d2edSShaohui Xie /* Read device revision and ID */ 32402b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 32502b5d2edSShaohui Xie debug("Retimer version id = 0x%x\n", reg); 32602b5d2edSShaohui Xie 32702b5d2edSShaohui Xie /* Enable Broadcast. All writes target all channel register sets */ 32802b5d2edSShaohui Xie reg = 0x0c; 32902b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 33002b5d2edSShaohui Xie 33102b5d2edSShaohui Xie /* Reset Channel Registers */ 33202b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 33302b5d2edSShaohui Xie reg |= 0x4; 33402b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 33502b5d2edSShaohui Xie 33602b5d2edSShaohui Xie /* Enable override divider select and Enable Override Output Mux */ 33702b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 33802b5d2edSShaohui Xie reg |= 0x24; 33902b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 34002b5d2edSShaohui Xie 34102b5d2edSShaohui Xie /* Select VCO Divider to full rate (000) */ 34202b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 34302b5d2edSShaohui Xie reg &= 0x8f; 34402b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 34502b5d2edSShaohui Xie 34602b5d2edSShaohui Xie /* Selects active PFD MUX Input as Re-timed Data (001) */ 34702b5d2edSShaohui Xie i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 34802b5d2edSShaohui Xie reg &= 0x3f; 34902b5d2edSShaohui Xie reg |= 0x20; 35002b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 35102b5d2edSShaohui Xie 35202b5d2edSShaohui Xie /* Set data rate as 10.3125 Gbps */ 35302b5d2edSShaohui Xie reg = 0x0; 35402b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 35502b5d2edSShaohui Xie reg = 0xb2; 35602b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 35702b5d2edSShaohui Xie reg = 0x90; 35802b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 35902b5d2edSShaohui Xie reg = 0xb3; 36002b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 36102b5d2edSShaohui Xie reg = 0xcd; 36202b5d2edSShaohui Xie i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 363ec44289dSWenbin Song 364ec44289dSWenbin Song /* Return the default channel */ 365ec44289dSWenbin Song select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 36602b5d2edSShaohui Xie } 36702b5d2edSShaohui Xie 36802b5d2edSShaohui Xie int board_early_init_f(void) 36902b5d2edSShaohui Xie { 3705a7c40beSQianyu Gong #ifdef CONFIG_HAS_FSL_XHCI_USB 3715a7c40beSQianyu Gong struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 3725a7c40beSQianyu Gong u32 usb_pwrfault; 3735a7c40beSQianyu Gong #endif 3748c35cc3bSShaohui Xie #ifdef CONFIG_LPUART 3758c35cc3bSShaohui Xie u8 uart; 3768c35cc3bSShaohui Xie #endif 377581ff00bSQianyu Gong 378581ff00bSQianyu Gong #ifdef CONFIG_SYS_I2C_EARLY_INIT 379581ff00bSQianyu Gong i2c_early_init_f(); 380581ff00bSQianyu Gong #endif 38102b5d2edSShaohui Xie fsl_lsch2_early_init_f(); 3825a7c40beSQianyu Gong 3835a7c40beSQianyu Gong #ifdef CONFIG_HAS_FSL_XHCI_USB 3845a7c40beSQianyu Gong out_be32(&scfg->rcwpmuxcr0, 0x3333); 3855a7c40beSQianyu Gong out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 3865a7c40beSQianyu Gong usb_pwrfault = 3873e06ba8fSShaohui Xie (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | 3883e06ba8fSShaohui Xie (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | 3895a7c40beSQianyu Gong (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); 3905a7c40beSQianyu Gong out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 3915a7c40beSQianyu Gong #endif 3925a7c40beSQianyu Gong 3938c35cc3bSShaohui Xie #ifdef CONFIG_LPUART 3948c35cc3bSShaohui Xie /* We use lpuart0 as system console */ 3958c35cc3bSShaohui Xie uart = QIXIS_READ(brdcfg[14]); 3968c35cc3bSShaohui Xie uart &= ~CFG_UART_MUX_MASK; 3978c35cc3bSShaohui Xie uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; 3988c35cc3bSShaohui Xie QIXIS_WRITE(brdcfg[14], uart); 3998c35cc3bSShaohui Xie #endif 40002b5d2edSShaohui Xie 40102b5d2edSShaohui Xie return 0; 40202b5d2edSShaohui Xie } 40302b5d2edSShaohui Xie 40402b5d2edSShaohui Xie #ifdef CONFIG_FSL_DEEP_SLEEP 40502b5d2edSShaohui Xie /* determine if it is a warm boot */ 40602b5d2edSShaohui Xie bool is_warm_boot(void) 40702b5d2edSShaohui Xie { 40802b5d2edSShaohui Xie #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 40902b5d2edSShaohui Xie struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 41002b5d2edSShaohui Xie 41102b5d2edSShaohui Xie if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 41202b5d2edSShaohui Xie return 1; 41302b5d2edSShaohui Xie 41402b5d2edSShaohui Xie return 0; 41502b5d2edSShaohui Xie } 41602b5d2edSShaohui Xie #endif 41702b5d2edSShaohui Xie 41802b5d2edSShaohui Xie int config_board_mux(int ctrl_type) 41902b5d2edSShaohui Xie { 42002b5d2edSShaohui Xie u8 reg14; 42102b5d2edSShaohui Xie 42202b5d2edSShaohui Xie reg14 = QIXIS_READ(brdcfg[14]); 42302b5d2edSShaohui Xie 42402b5d2edSShaohui Xie switch (ctrl_type) { 42502b5d2edSShaohui Xie case MUX_TYPE_GPIO: 42602b5d2edSShaohui Xie reg14 = (reg14 & (~0x30)) | 0x20; 42702b5d2edSShaohui Xie break; 42802b5d2edSShaohui Xie default: 42902b5d2edSShaohui Xie puts("Unsupported mux interface type\n"); 43002b5d2edSShaohui Xie return -1; 43102b5d2edSShaohui Xie } 43202b5d2edSShaohui Xie 43302b5d2edSShaohui Xie QIXIS_WRITE(brdcfg[14], reg14); 43402b5d2edSShaohui Xie 43502b5d2edSShaohui Xie return 0; 43602b5d2edSShaohui Xie } 43702b5d2edSShaohui Xie 43802b5d2edSShaohui Xie int config_serdes_mux(void) 43902b5d2edSShaohui Xie { 44002b5d2edSShaohui Xie return 0; 44102b5d2edSShaohui Xie } 44202b5d2edSShaohui Xie 44302b5d2edSShaohui Xie 44402b5d2edSShaohui Xie #ifdef CONFIG_MISC_INIT_R 44502b5d2edSShaohui Xie int misc_init_r(void) 44602b5d2edSShaohui Xie { 44702b5d2edSShaohui Xie if (hwconfig("gpio")) 44802b5d2edSShaohui Xie config_board_mux(MUX_TYPE_GPIO); 44902b5d2edSShaohui Xie 45002b5d2edSShaohui Xie return 0; 45102b5d2edSShaohui Xie } 45202b5d2edSShaohui Xie #endif 45302b5d2edSShaohui Xie 45402b5d2edSShaohui Xie int board_init(void) 45502b5d2edSShaohui Xie { 456b392a6d4SHou Zhiqiang #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 457b392a6d4SHou Zhiqiang erratum_a010315(); 458b392a6d4SHou Zhiqiang #endif 459b392a6d4SHou Zhiqiang 46002b5d2edSShaohui Xie select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 46102b5d2edSShaohui Xie board_retimer_init(); 46202b5d2edSShaohui Xie 46302b5d2edSShaohui Xie #ifdef CONFIG_SYS_FSL_SERDES 46402b5d2edSShaohui Xie config_serdes_mux(); 46502b5d2edSShaohui Xie #endif 46602b5d2edSShaohui Xie 467e1b09290SHou Zhiqiang #ifdef CONFIG_FSL_LS_PPA 468e1b09290SHou Zhiqiang ppa_init(); 469e1b09290SHou Zhiqiang #endif 470e1b09290SHou Zhiqiang 47102b5d2edSShaohui Xie return 0; 47202b5d2edSShaohui Xie } 47302b5d2edSShaohui Xie 47402b5d2edSShaohui Xie #ifdef CONFIG_OF_BOARD_SETUP 47502b5d2edSShaohui Xie int ft_board_setup(void *blob, bd_t *bd) 47602b5d2edSShaohui Xie { 47758e4ad1dSShaohui Xie u64 base[CONFIG_NR_DRAM_BANKS]; 47858e4ad1dSShaohui Xie u64 size[CONFIG_NR_DRAM_BANKS]; 4798401c710SQianyu Gong u8 reg; 48058e4ad1dSShaohui Xie 48158e4ad1dSShaohui Xie /* fixup DT for the two DDR banks */ 48258e4ad1dSShaohui Xie base[0] = gd->bd->bi_dram[0].start; 48358e4ad1dSShaohui Xie size[0] = gd->bd->bi_dram[0].size; 48458e4ad1dSShaohui Xie base[1] = gd->bd->bi_dram[1].start; 48558e4ad1dSShaohui Xie size[1] = gd->bd->bi_dram[1].size; 48658e4ad1dSShaohui Xie 48758e4ad1dSShaohui Xie fdt_fixup_memory_banks(blob, base, size, 2); 48802b5d2edSShaohui Xie ft_cpu_setup(blob, bd); 48902b5d2edSShaohui Xie 49002b5d2edSShaohui Xie #ifdef CONFIG_SYS_DPAA_FMAN 49102b5d2edSShaohui Xie fdt_fixup_fman_ethernet(blob); 49202b5d2edSShaohui Xie fdt_fixup_board_enet(blob); 49302b5d2edSShaohui Xie #endif 4948401c710SQianyu Gong 495dc29a4c1SLaurentiu Tudor fdt_fixup_icid(blob); 496dc29a4c1SLaurentiu Tudor 4978401c710SQianyu Gong reg = QIXIS_READ(brdcfg[0]); 4988401c710SQianyu Gong reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 4998401c710SQianyu Gong 5008401c710SQianyu Gong /* Disable IFC if QSPI is enabled */ 5018401c710SQianyu Gong if (reg == 0xF) 5028401c710SQianyu Gong do_fixup_by_compat(blob, "fsl,ifc", 5038401c710SQianyu Gong "status", "disabled", 8 + 1, 1); 5048401c710SQianyu Gong 50502b5d2edSShaohui Xie return 0; 50602b5d2edSShaohui Xie } 50702b5d2edSShaohui Xie #endif 50802b5d2edSShaohui Xie 50902b5d2edSShaohui Xie u8 flash_read8(void *addr) 51002b5d2edSShaohui Xie { 51102b5d2edSShaohui Xie return __raw_readb(addr + 1); 51202b5d2edSShaohui Xie } 51302b5d2edSShaohui Xie 51402b5d2edSShaohui Xie void flash_write16(u16 val, void *addr) 51502b5d2edSShaohui Xie { 51602b5d2edSShaohui Xie u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 51702b5d2edSShaohui Xie 51802b5d2edSShaohui Xie __raw_writew(shftval, addr); 51902b5d2edSShaohui Xie } 52002b5d2edSShaohui Xie 52102b5d2edSShaohui Xie u16 flash_read16(void *addr) 52202b5d2edSShaohui Xie { 52302b5d2edSShaohui Xie u16 val = __raw_readw(addr); 52402b5d2edSShaohui Xie 52502b5d2edSShaohui Xie return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 52602b5d2edSShaohui Xie } 527*8aa6b17aSRajesh Bhagat 528*8aa6b17aSRajesh Bhagat #ifdef CONFIG_TFABOOT 529*8aa6b17aSRajesh Bhagat void *env_sf_get_env_addr(void) 530*8aa6b17aSRajesh Bhagat { 531*8aa6b17aSRajesh Bhagat return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); 532*8aa6b17aSRajesh Bhagat } 533*8aa6b17aSRajesh Bhagat #endif 534