1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 9 extern void erratum_a008850_post(void); 10 11 struct board_specific_parameters { 12 u32 n_ranks; 13 u32 datarate_mhz_high; 14 u32 rank_gb; 15 u32 clk_adjust; 16 u32 wrlvl_start; 17 u32 wrlvl_ctl_2; 18 u32 wrlvl_ctl_3; 19 u32 cpo_override; 20 u32 write_data_delay; 21 u32 force_2t; 22 }; 23 24 /* 25 * These tables contain all valid speeds we want to override with board 26 * specific parameters. datarate_mhz_high values need to be in ascending order 27 * for each n_ranks group. 28 */ 29 static const struct board_specific_parameters udimm0[] = { 30 /* 31 * memory controller 0 32 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 33 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 34 */ 35 #ifdef CONFIG_SYS_FSL_DDR4 36 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 37 {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 38 {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, 39 {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, 40 {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, 41 #elif defined(CONFIG_SYS_FSL_DDR3) 42 {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 43 {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 44 {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 45 {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 46 {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 47 {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 48 {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 49 {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 50 {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 51 #else 52 #error DDR type not defined 53 #endif 54 {} 55 }; 56 57 static const struct board_specific_parameters *udimms[] = { 58 udimm0, 59 }; 60 61 #endif 62