1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 10 struct board_specific_parameters { 11 u32 n_ranks; 12 u32 datarate_mhz_high; 13 u32 rank_gb; 14 u32 clk_adjust; 15 u32 wrlvl_start; 16 u32 wrlvl_ctl_2; 17 u32 wrlvl_ctl_3; 18 u32 cpo_override; 19 u32 write_data_delay; 20 u32 force_2t; 21 }; 22 23 /* 24 * These tables contain all valid speeds we want to override with board 25 * specific parameters. datarate_mhz_high values need to be in ascending order 26 * for each n_ranks group. 27 */ 28 static const struct board_specific_parameters udimm0[] = { 29 /* 30 * memory controller 0 31 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 32 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 33 */ 34 #ifdef CONFIG_SYS_FSL_DDR4 35 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 36 {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, 37 {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, 38 {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, 39 {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, 40 #elif defined(CONFIG_SYS_FSL_DDR3) 41 {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 42 {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 43 {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 44 {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 45 {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 46 {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 47 {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 48 {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 49 {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 50 #else 51 #error DDR type not defined 52 #endif 53 {} 54 }; 55 56 static const struct board_specific_parameters *udimms[] = { 57 udimm0, 58 }; 59 60 #endif 61