1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <fsl_ddr_sdram.h>
8 #include <fsl_ddr_dimm_params.h>
9 #ifdef CONFIG_FSL_DEEP_SLEEP
10 #include <fsl_sleep.h>
11 #endif
12 #include <asm/arch/clock.h>
13 #include "ddr.h"
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 void fsl_ddr_board_options(memctl_options_t *popts,
18 			   dimm_params_t *pdimm,
19 			   unsigned int ctrl_num)
20 {
21 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 	ulong ddr_freq;
23 
24 	if (ctrl_num > 3) {
25 		printf("Not supported controller number %d\n", ctrl_num);
26 		return;
27 	}
28 	if (!pdimm->n_ranks)
29 		return;
30 
31 	pbsp = udimms[0];
32 
33 	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
34 	 * freqency and n_banks specified in board_specific_parameters table.
35 	 */
36 	ddr_freq = get_ddr_freq(0) / 1000000;
37 	while (pbsp->datarate_mhz_high) {
38 		if (pbsp->n_ranks == pdimm->n_ranks) {
39 			if (ddr_freq <= pbsp->datarate_mhz_high) {
40 				popts->clk_adjust = pbsp->clk_adjust;
41 				popts->wrlvl_start = pbsp->wrlvl_start;
42 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
43 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
44 				popts->cpo_override = pbsp->cpo_override;
45 				popts->write_data_delay =
46 					pbsp->write_data_delay;
47 				goto found;
48 			}
49 			pbsp_highest = pbsp;
50 		}
51 		pbsp++;
52 	}
53 
54 	if (pbsp_highest) {
55 		printf("Error: board specific timing not found for %lu MT/s\n",
56 		       ddr_freq);
57 		printf("Trying to use the highest speed (%u) parameters\n",
58 		       pbsp_highest->datarate_mhz_high);
59 		popts->clk_adjust = pbsp_highest->clk_adjust;
60 		popts->wrlvl_start = pbsp_highest->wrlvl_start;
61 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
62 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
63 	} else {
64 		panic("DIMM is not supported by this board");
65 	}
66 found:
67 	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
68 	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
69 
70 	/* force DDR bus width to 32 bits */
71 	popts->data_bus_width = 1;
72 	popts->otf_burst_chop_en = 0;
73 	popts->burst_length = DDR_BL8;
74 	popts->bstopre = 0;		/* enable auto precharge */
75 
76 	/*
77 	 * Factors to consider for half-strength driver enable:
78 	 *	- number of DIMMs installed
79 	 */
80 	popts->half_strength_driver_enable = 1;
81 	/*
82 	 * Write leveling override
83 	 */
84 	popts->wrlvl_override = 1;
85 	popts->wrlvl_sample = 0xf;
86 
87 	/*
88 	 * Rtt and Rtt_WR override
89 	 */
90 	popts->rtt_override = 0;
91 
92 	/* Enable ZQ calibration */
93 	popts->zq_en = 1;
94 
95 #ifdef CONFIG_SYS_FSL_DDR4
96 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
97 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
98 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
99 
100 	/* optimize cpo for erratum A-009942 */
101 	popts->cpo_sample = 0x59;
102 #else
103 	popts->cswl_override = DDR_CSWL_CS0;
104 
105 	/* DHC_EN =1, ODT = 75 Ohm */
106 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
107 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
108 #endif
109 }
110 
111 #ifdef CONFIG_TFABOOT
112 int fsl_initdram(void)
113 {
114 	gd->ram_size = tfa_get_dram_size();
115 	if (!gd->ram_size)
116 		gd->ram_size = fsl_ddr_sdram_size();
117 
118 	return 0;
119 }
120 #else
121 int fsl_initdram(void)
122 {
123 	phys_size_t dram_size;
124 
125 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
126 	gd->ram_size = fsl_ddr_sdram_size();
127 
128 	return 0;
129 #else
130 	puts("Initializing DDR....using SPD\n");
131 
132 	dram_size = fsl_ddr_sdram();
133 #endif
134 	erratum_a008850_post();
135 
136 #ifdef CONFIG_FSL_DEEP_SLEEP
137 	fsl_dp_ddr_restore();
138 #endif
139 
140 	gd->ram_size = dram_size;
141 
142 	return 0;
143 }
144 #endif
145