1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
15 #include <asm/arch/ls102xa_sata.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_csu.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_immap.h>
22 #include <netdev.h>
23 #include <fsl_mdio.h>
24 #include <tsec.h>
25 #include <fsl_sec.h>
26 #include <fsl_devdis.h>
27 #include <spl.h>
28 #include "../common/sleep.h"
29 #ifdef CONFIG_U_QE
30 #include <fsl_qe.h>
31 #endif
32 #include <fsl_validate.h>
33 
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #define VERSION_MASK		0x00FF
38 #define BANK_MASK		0x0001
39 #define CONFIG_RESET		0x1
40 #define INIT_RESET		0x1
41 
42 #define CPLD_SET_MUX_SERDES	0x20
43 #define CPLD_SET_BOOT_BANK	0x40
44 
45 #define BOOT_FROM_UPPER_BANK	0x0
46 #define BOOT_FROM_LOWER_BANK	0x1
47 
48 #define LANEB_SATA		(0x01)
49 #define LANEB_SGMII1		(0x02)
50 #define LANEC_SGMII1		(0x04)
51 #define LANEC_PCIEX1		(0x08)
52 #define LANED_PCIEX2		(0x10)
53 #define LANED_SGMII2		(0x20)
54 
55 #define MASK_LANE_B		0x1
56 #define MASK_LANE_C		0x2
57 #define MASK_LANE_D		0x4
58 #define MASK_SGMII		0x8
59 
60 #define KEEP_STATUS		0x0
61 #define NEED_RESET		0x1
62 
63 #define SOFT_MUX_ON_I2C3_IFC	0x2
64 #define SOFT_MUX_ON_CAN3_USB2	0x8
65 #define SOFT_MUX_ON_QE_LCD	0x10
66 
67 #define PIN_I2C3_IFC_MUX_I2C3	0x0
68 #define PIN_I2C3_IFC_MUX_IFC	0x1
69 #define PIN_CAN3_USB2_MUX_USB2	0x0
70 #define PIN_CAN3_USB2_MUX_CAN3	0x1
71 #define PIN_QE_LCD_MUX_LCD	0x0
72 #define PIN_QE_LCD_MUX_QE	0x1
73 
74 struct cpld_data {
75 	u8 cpld_ver;		/* cpld revision */
76 	u8 cpld_ver_sub;	/* cpld sub revision */
77 	u8 pcba_ver;		/* pcb revision number */
78 	u8 system_rst;		/* reset system by cpld */
79 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
80 	u8 cfg_rcw_src1;	/* Reset config word 1 */
81 	u8 cfg_rcw_src2;	/* Reset config word 2 */
82 	u8 vbank;		/* Flash bank selection Control */
83 	u8 gpio;		/* GPIO for TWR-ELEV */
84 	u8 i2c3_ifc_mux;
85 	u8 mux_spi2;
86 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
87 	u8 qe_lcd_mux;		/* QE and LCD Selection */
88 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
89 	u8 global_rst;		/* reset with init CPLD reg to default */
90 	u8 rev1;		/* Reserved */
91 	u8 rev2;		/* Reserved */
92 };
93 
94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
95 static void convert_serdes_mux(int type, int need_reset);
96 
97 void cpld_show(void)
98 {
99 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
100 
101 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
102 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
103 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
104 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
105 	       in_8(&cpld_data->vbank) & BANK_MASK);
106 
107 #ifdef CONFIG_DEBUG
108 	printf("soft_mux_on =%x\n",
109 	       in_8(&cpld_data->soft_mux_on));
110 	printf("cfg_rcw_src1 =%x\n",
111 	       in_8(&cpld_data->cfg_rcw_src1));
112 	printf("cfg_rcw_src2 =%x\n",
113 	       in_8(&cpld_data->cfg_rcw_src2));
114 	printf("vbank =%x\n",
115 	       in_8(&cpld_data->vbank));
116 	printf("gpio =%x\n",
117 	       in_8(&cpld_data->gpio));
118 	printf("i2c3_ifc_mux =%x\n",
119 	       in_8(&cpld_data->i2c3_ifc_mux));
120 	printf("mux_spi2 =%x\n",
121 	       in_8(&cpld_data->mux_spi2));
122 	printf("can3_usb2_mux =%x\n",
123 	       in_8(&cpld_data->can3_usb2_mux));
124 	printf("qe_lcd_mux =%x\n",
125 	       in_8(&cpld_data->qe_lcd_mux));
126 	printf("serdes_mux =%x\n",
127 	       in_8(&cpld_data->serdes_mux));
128 #endif
129 }
130 #endif
131 
132 int checkboard(void)
133 {
134 	puts("Board: LS1021ATWR\n");
135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
136 	cpld_show();
137 #endif
138 
139 	return 0;
140 }
141 
142 void ddrmc_init(void)
143 {
144 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
145 	u32 temp_sdram_cfg, tmp;
146 
147 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
148 
149 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
150 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
151 
152 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
153 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
154 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
155 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
156 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
157 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
158 
159 #ifdef CONFIG_DEEP_SLEEP
160 	if (is_warm_boot()) {
161 		out_be32(&ddr->sdram_cfg_2,
162 			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
163 		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
164 		out_be32(&ddr->init_ext_addr, (1 << 31));
165 
166 		/* DRAM VRef will not be trained */
167 		out_be32(&ddr->ddr_cdr2,
168 			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
169 	} else
170 #endif
171 	{
172 		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
173 		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
174 	}
175 
176 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
177 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
178 
179 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
180 
181 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
182 
183 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
184 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
185 
186 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
187 
188 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
189 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
190 
191 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
192 
193 	/* DDR erratum A-009942 */
194 	tmp = in_be32(&ddr->debug[28]);
195 	out_be32(&ddr->debug[28], tmp | 0x0070006f);
196 
197 	udelay(1);
198 
199 #ifdef CONFIG_DEEP_SLEEP
200 	if (is_warm_boot()) {
201 		/* enter self-refresh */
202 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
203 		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
204 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
205 
206 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
207 	} else
208 #endif
209 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
210 
211 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
212 
213 #ifdef CONFIG_DEEP_SLEEP
214 	if (is_warm_boot()) {
215 		/* exit self-refresh */
216 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
217 		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
218 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
219 	}
220 #endif
221 }
222 
223 int dram_init(void)
224 {
225 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
226 	ddrmc_init();
227 #endif
228 
229 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
230 
231 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
232 	fsl_dp_resume();
233 #endif
234 
235 	return 0;
236 }
237 
238 #ifdef CONFIG_FSL_ESDHC
239 struct fsl_esdhc_cfg esdhc_cfg[1] = {
240 	{CONFIG_SYS_FSL_ESDHC_ADDR},
241 };
242 
243 int board_mmc_init(bd_t *bis)
244 {
245 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
246 
247 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
248 }
249 #endif
250 
251 int board_eth_init(bd_t *bis)
252 {
253 #ifdef CONFIG_TSEC_ENET
254 	struct fsl_pq_mdio_info mdio_info;
255 	struct tsec_info_struct tsec_info[4];
256 	int num = 0;
257 
258 #ifdef CONFIG_TSEC1
259 	SET_STD_TSEC_INFO(tsec_info[num], 1);
260 	if (is_serdes_configured(SGMII_TSEC1)) {
261 		puts("eTSEC1 is in sgmii mode.\n");
262 		tsec_info[num].flags |= TSEC_SGMII;
263 	}
264 	num++;
265 #endif
266 #ifdef CONFIG_TSEC2
267 	SET_STD_TSEC_INFO(tsec_info[num], 2);
268 	if (is_serdes_configured(SGMII_TSEC2)) {
269 		puts("eTSEC2 is in sgmii mode.\n");
270 		tsec_info[num].flags |= TSEC_SGMII;
271 	}
272 	num++;
273 #endif
274 #ifdef CONFIG_TSEC3
275 	SET_STD_TSEC_INFO(tsec_info[num], 3);
276 	tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
277 	num++;
278 #endif
279 	if (!num) {
280 		printf("No TSECs initialized\n");
281 		return 0;
282 	}
283 
284 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
285 	mdio_info.name = DEFAULT_MII_NAME;
286 	fsl_pq_mdio_init(bis, &mdio_info);
287 
288 	tsec_eth_init(bis, tsec_info, num);
289 #endif
290 
291 	return pci_eth_init(bis);
292 }
293 
294 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
295 int config_serdes_mux(void)
296 {
297 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
298 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
299 
300 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
301 	switch (protocol) {
302 	case 0x10:
303 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
304 		convert_serdes_mux(LANED_PCIEX2 |
305 				LANEC_PCIEX1, KEEP_STATUS);
306 		break;
307 	case 0x20:
308 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
309 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
310 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
311 		break;
312 	case 0x30:
313 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
314 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
315 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
316 		break;
317 	case 0x70:
318 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
319 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
320 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
321 		break;
322 	}
323 
324 	return 0;
325 }
326 #endif
327 
328 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
329 int config_board_mux(void)
330 {
331 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
332 	int conflict_flag;
333 
334 	conflict_flag = 0;
335 	if (hwconfig("i2c3")) {
336 		conflict_flag++;
337 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
338 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
339 	}
340 
341 	if (hwconfig("ifc")) {
342 		conflict_flag++;
343 		/* some signals can not enable simultaneous*/
344 		if (conflict_flag > 1)
345 			goto conflict;
346 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
347 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
348 	}
349 
350 	conflict_flag = 0;
351 	if (hwconfig("usb2")) {
352 		conflict_flag++;
353 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
354 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
355 	}
356 
357 	if (hwconfig("can3")) {
358 		conflict_flag++;
359 		/* some signals can not enable simultaneous*/
360 		if (conflict_flag > 1)
361 			goto conflict;
362 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
363 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
364 	}
365 
366 	conflict_flag = 0;
367 	if (hwconfig("lcd")) {
368 		conflict_flag++;
369 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
370 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
371 	}
372 
373 	if (hwconfig("qe")) {
374 		conflict_flag++;
375 		/* some signals can not enable simultaneous*/
376 		if (conflict_flag > 1)
377 			goto conflict;
378 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
379 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
380 	}
381 
382 	return 0;
383 
384 conflict:
385 	printf("WARNING: pin conflict! MUX setting may failed!\n");
386 	return 0;
387 }
388 #endif
389 
390 int board_early_init_f(void)
391 {
392 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
393 
394 #ifdef CONFIG_TSEC_ENET
395 	/* clear BD & FR bits for BE BD's and frame data */
396 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
397 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
398 #endif
399 
400 #ifdef CONFIG_FSL_IFC
401 	init_early_memctl_regs();
402 #endif
403 
404 	arch_soc_init();
405 
406 #if defined(CONFIG_DEEP_SLEEP)
407 	if (is_warm_boot()) {
408 		timer_init();
409 		dram_init();
410 	}
411 #endif
412 
413 	return 0;
414 }
415 
416 #ifdef CONFIG_SPL_BUILD
417 void board_init_f(ulong dummy)
418 {
419 	void (*second_uboot)(void);
420 
421 	/* Clear the BSS */
422 	memset(__bss_start, 0, __bss_end - __bss_start);
423 
424 	get_clocks();
425 
426 #if defined(CONFIG_DEEP_SLEEP)
427 	if (is_warm_boot())
428 		fsl_dp_disable_console();
429 #endif
430 
431 	preloader_console_init();
432 
433 	dram_init();
434 
435 	/* Allow OCRAM access permission as R/W */
436 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
437 	enable_layerscape_ns_access();
438 	enable_layerscape_ns_access();
439 #endif
440 
441 	/*
442 	 * if it is woken up from deep sleep, then jump to second
443 	 * stage uboot and continue executing without recopying
444 	 * it from SD since it has already been reserved in memeory
445 	 * in last boot.
446 	 */
447 	if (is_warm_boot()) {
448 		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
449 		second_uboot();
450 	}
451 
452 	board_init_r(NULL, 0);
453 }
454 #endif
455 
456 #ifdef CONFIG_DEEP_SLEEP
457 /* program the regulator (MC34VR500) to support deep sleep */
458 void ls1twr_program_regulator(void)
459 {
460 	unsigned int i2c_bus;
461 	u8 i2c_device_id;
462 
463 #define LS1TWR_I2C_BUS_MC34VR500	1
464 #define MC34VR500_ADDR			0x8
465 #define MC34VR500_DEVICEID		0x4
466 #define MC34VR500_DEVICEID_MASK		0x0f
467 
468 	i2c_bus = i2c_get_bus_num();
469 	i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
470 	i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
471 					MC34VR500_DEVICEID_MASK;
472 	if (i2c_device_id != MC34VR500_DEVICEID) {
473 		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
474 		return;
475 	}
476 
477 	i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
478 	i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
479 	i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
480 	i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
481 	i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
482 
483 	i2c_set_bus_num(i2c_bus);
484 }
485 #endif
486 
487 int board_init(void)
488 {
489 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
490 	erratum_a010315();
491 #endif
492 
493 #ifndef CONFIG_SYS_FSL_NO_SERDES
494 	fsl_serdes_init();
495 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
496 	config_serdes_mux();
497 #endif
498 #endif
499 
500 	ls102xa_smmu_stream_id_init();
501 
502 #ifdef CONFIG_U_QE
503 	u_qe_init();
504 #endif
505 
506 #ifdef CONFIG_DEEP_SLEEP
507 	ls1twr_program_regulator();
508 #endif
509 	return 0;
510 }
511 
512 #if defined(CONFIG_SPL_BUILD)
513 void spl_board_init(void)
514 {
515 	ls102xa_smmu_stream_id_init();
516 }
517 #endif
518 
519 #ifdef CONFIG_BOARD_LATE_INIT
520 int board_late_init(void)
521 {
522 #ifdef CONFIG_SCSI_AHCI_PLAT
523 	ls1021a_sata_init();
524 #endif
525 #ifdef CONFIG_CHAIN_OF_TRUST
526 	fsl_setenv_chain_of_trust();
527 #endif
528 
529 	return 0;
530 }
531 #endif
532 
533 #if defined(CONFIG_MISC_INIT_R)
534 int misc_init_r(void)
535 {
536 #ifdef CONFIG_FSL_DEVICE_DISABLE
537 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
538 #endif
539 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
540 	config_board_mux();
541 #endif
542 
543 #ifdef CONFIG_FSL_CAAM
544 	return sec_init();
545 #endif
546 }
547 #endif
548 
549 #if defined(CONFIG_DEEP_SLEEP)
550 void board_sleep_prepare(void)
551 {
552 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
553 	enable_layerscape_ns_access();
554 #endif
555 }
556 #endif
557 
558 int ft_board_setup(void *blob, bd_t *bd)
559 {
560 	ft_cpu_setup(blob, bd);
561 
562 #ifdef CONFIG_PCI
563 	ft_pci_setup(blob, bd);
564 #endif
565 
566 	return 0;
567 }
568 
569 u8 flash_read8(void *addr)
570 {
571 	return __raw_readb(addr + 1);
572 }
573 
574 void flash_write16(u16 val, void *addr)
575 {
576 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
577 
578 	__raw_writew(shftval, addr);
579 }
580 
581 u16 flash_read16(void *addr)
582 {
583 	u16 val = __raw_readw(addr);
584 
585 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
586 }
587 
588 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
589 static void convert_flash_bank(char bank)
590 {
591 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
592 
593 	printf("Now switch to boot from flash bank %d.\n", bank);
594 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
595 	cpld_data->vbank = bank;
596 
597 	printf("Reset board to enable configuration.\n");
598 	cpld_data->system_rst = CONFIG_RESET;
599 }
600 
601 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
602 			  char * const argv[])
603 {
604 	if (argc != 2)
605 		return CMD_RET_USAGE;
606 	if (strcmp(argv[1], "0") == 0)
607 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
608 	else if (strcmp(argv[1], "1") == 0)
609 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
610 	else
611 		return CMD_RET_USAGE;
612 
613 	return 0;
614 }
615 
616 U_BOOT_CMD(
617 	boot_bank, 2, 0, flash_bank_cmd,
618 	"Flash bank Selection Control",
619 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
620 );
621 
622 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
623 			  char * const argv[])
624 {
625 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
626 
627 	if (argc > 2)
628 		return CMD_RET_USAGE;
629 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
630 		cpld_data->system_rst = CONFIG_RESET;
631 	else if (strcmp(argv[1], "init") == 0)
632 		cpld_data->global_rst = INIT_RESET;
633 	else
634 		return CMD_RET_USAGE;
635 
636 	return 0;
637 }
638 
639 U_BOOT_CMD(
640 	cpld_reset, 2, 0, cpld_reset_cmd,
641 	"Reset via CPLD",
642 	"conf\n"
643 	"	-reset with current CPLD configuration\n"
644 	"init\n"
645 	"	-reset and initial CPLD configuration with default value"
646 
647 );
648 
649 static void convert_serdes_mux(int type, int need_reset)
650 {
651 	char current_serdes;
652 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
653 
654 	current_serdes = cpld_data->serdes_mux;
655 
656 	switch (type) {
657 	case LANEB_SATA:
658 		current_serdes &= ~MASK_LANE_B;
659 		break;
660 	case LANEB_SGMII1:
661 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
662 		break;
663 	case LANEC_SGMII1:
664 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
665 		break;
666 	case LANED_SGMII2:
667 		current_serdes |= MASK_LANE_D;
668 		break;
669 	case LANEC_PCIEX1:
670 		current_serdes |= MASK_LANE_C;
671 		break;
672 	case (LANED_PCIEX2 | LANEC_PCIEX1):
673 		current_serdes |= MASK_LANE_C;
674 		current_serdes &= ~MASK_LANE_D;
675 		break;
676 	default:
677 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
678 		return;
679 	}
680 
681 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
682 	cpld_data->serdes_mux = current_serdes;
683 
684 	if (need_reset == 1) {
685 		printf("Reset board to enable configuration\n");
686 		cpld_data->system_rst = CONFIG_RESET;
687 	}
688 }
689 
690 void print_serdes_mux(void)
691 {
692 	char current_serdes;
693 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
694 
695 	current_serdes = cpld_data->serdes_mux;
696 
697 	printf("Serdes Lane B: ");
698 	if ((current_serdes & MASK_LANE_B) == 0)
699 		printf("SATA,\n");
700 	else
701 		printf("SGMII 1,\n");
702 
703 	printf("Serdes Lane C: ");
704 	if ((current_serdes & MASK_LANE_C) == 0)
705 		printf("SGMII 1,\n");
706 	else
707 		printf("PCIe,\n");
708 
709 	printf("Serdes Lane D: ");
710 	if ((current_serdes & MASK_LANE_D) == 0)
711 		printf("PCIe,\n");
712 	else
713 		printf("SGMII 2,\n");
714 
715 	printf("SGMII 1 is on lane ");
716 	if ((current_serdes & MASK_SGMII) == 0)
717 		printf("C.\n");
718 	else
719 		printf("B.\n");
720 }
721 
722 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
723 			  char * const argv[])
724 {
725 	if (argc != 2)
726 		return CMD_RET_USAGE;
727 	if (strcmp(argv[1], "sata") == 0) {
728 		printf("Set serdes lane B to SATA.\n");
729 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
730 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
731 		printf("Set serdes lane B to SGMII 1.\n");
732 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
733 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
734 		printf("Set serdes lane C to SGMII 1.\n");
735 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
736 	} else if (strcmp(argv[1], "sgmii2") == 0) {
737 		printf("Set serdes lane D to SGMII 2.\n");
738 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
739 	} else if (strcmp(argv[1], "pciex1") == 0) {
740 		printf("Set serdes lane C to PCIe X1.\n");
741 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
742 	} else if (strcmp(argv[1], "pciex2") == 0) {
743 		printf("Set serdes lane C & lane D to PCIe X2.\n");
744 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
745 	} else if (strcmp(argv[1], "show") == 0) {
746 		print_serdes_mux();
747 	} else {
748 		return CMD_RET_USAGE;
749 	}
750 
751 	return 0;
752 }
753 
754 U_BOOT_CMD(
755 	lane_bank, 2, 0, serdes_mux_cmd,
756 	"Multiplexed function setting for SerDes Lanes",
757 	"sata\n"
758 	"	-change lane B to sata\n"
759 	"lane_bank sgmii1b\n"
760 	"	-change lane B to SGMII1\n"
761 	"lane_bank sgmii1c\n"
762 	"	-change lane C to SGMII1\n"
763 	"lane_bank sgmii2\n"
764 	"	-change lane D to SGMII2\n"
765 	"lane_bank pciex1\n"
766 	"	-change lane C to PCIeX1\n"
767 	"lane_bank pciex2\n"
768 	"	-change lane C & lane D to PCIeX2\n"
769 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
770 );
771 #endif
772