1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ls102xa_stream_id.h> 14 #include <asm/arch/ls102xa_devdis.h> 15 #include <asm/arch/ls102xa_sata.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <fsl_csu.h> 19 #include <fsl_esdhc.h> 20 #include <fsl_ifc.h> 21 #include <fsl_immap.h> 22 #include <netdev.h> 23 #include <fsl_mdio.h> 24 #include <tsec.h> 25 #include <fsl_sec.h> 26 #include <fsl_devdis.h> 27 #include <spl.h> 28 #include "../common/sleep.h" 29 #ifdef CONFIG_U_QE 30 #include "../../../drivers/qe/qe.h" 31 #endif 32 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define VERSION_MASK 0x00FF 37 #define BANK_MASK 0x0001 38 #define CONFIG_RESET 0x1 39 #define INIT_RESET 0x1 40 41 #define CPLD_SET_MUX_SERDES 0x20 42 #define CPLD_SET_BOOT_BANK 0x40 43 44 #define BOOT_FROM_UPPER_BANK 0x0 45 #define BOOT_FROM_LOWER_BANK 0x1 46 47 #define LANEB_SATA (0x01) 48 #define LANEB_SGMII1 (0x02) 49 #define LANEC_SGMII1 (0x04) 50 #define LANEC_PCIEX1 (0x08) 51 #define LANED_PCIEX2 (0x10) 52 #define LANED_SGMII2 (0x20) 53 54 #define MASK_LANE_B 0x1 55 #define MASK_LANE_C 0x2 56 #define MASK_LANE_D 0x4 57 #define MASK_SGMII 0x8 58 59 #define KEEP_STATUS 0x0 60 #define NEED_RESET 0x1 61 62 #define SOFT_MUX_ON_I2C3_IFC 0x2 63 #define SOFT_MUX_ON_CAN3_USB2 0x8 64 #define SOFT_MUX_ON_QE_LCD 0x10 65 66 #define PIN_I2C3_IFC_MUX_I2C3 0x0 67 #define PIN_I2C3_IFC_MUX_IFC 0x1 68 #define PIN_CAN3_USB2_MUX_USB2 0x0 69 #define PIN_CAN3_USB2_MUX_CAN3 0x1 70 #define PIN_QE_LCD_MUX_LCD 0x0 71 #define PIN_QE_LCD_MUX_QE 0x1 72 73 struct cpld_data { 74 u8 cpld_ver; /* cpld revision */ 75 u8 cpld_ver_sub; /* cpld sub revision */ 76 u8 pcba_ver; /* pcb revision number */ 77 u8 system_rst; /* reset system by cpld */ 78 u8 soft_mux_on; /* CPLD override physical switches Enable */ 79 u8 cfg_rcw_src1; /* Reset config word 1 */ 80 u8 cfg_rcw_src2; /* Reset config word 2 */ 81 u8 vbank; /* Flash bank selection Control */ 82 u8 gpio; /* GPIO for TWR-ELEV */ 83 u8 i2c3_ifc_mux; 84 u8 mux_spi2; 85 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 86 u8 qe_lcd_mux; /* QE and LCD Selection */ 87 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 88 u8 global_rst; /* reset with init CPLD reg to default */ 89 u8 rev1; /* Reserved */ 90 u8 rev2; /* Reserved */ 91 }; 92 93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 94 static void convert_serdes_mux(int type, int need_reset); 95 96 void cpld_show(void) 97 { 98 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 99 100 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 101 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 102 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 103 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 104 in_8(&cpld_data->vbank) & BANK_MASK); 105 106 #ifdef CONFIG_DEBUG 107 printf("soft_mux_on =%x\n", 108 in_8(&cpld_data->soft_mux_on)); 109 printf("cfg_rcw_src1 =%x\n", 110 in_8(&cpld_data->cfg_rcw_src1)); 111 printf("cfg_rcw_src2 =%x\n", 112 in_8(&cpld_data->cfg_rcw_src2)); 113 printf("vbank =%x\n", 114 in_8(&cpld_data->vbank)); 115 printf("gpio =%x\n", 116 in_8(&cpld_data->gpio)); 117 printf("i2c3_ifc_mux =%x\n", 118 in_8(&cpld_data->i2c3_ifc_mux)); 119 printf("mux_spi2 =%x\n", 120 in_8(&cpld_data->mux_spi2)); 121 printf("can3_usb2_mux =%x\n", 122 in_8(&cpld_data->can3_usb2_mux)); 123 printf("qe_lcd_mux =%x\n", 124 in_8(&cpld_data->qe_lcd_mux)); 125 printf("serdes_mux =%x\n", 126 in_8(&cpld_data->serdes_mux)); 127 #endif 128 } 129 #endif 130 131 int checkboard(void) 132 { 133 puts("Board: LS1021ATWR\n"); 134 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 135 cpld_show(); 136 #endif 137 138 return 0; 139 } 140 141 unsigned int get_soc_major_rev(void) 142 { 143 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 144 unsigned int svr, major; 145 146 svr = in_be32(&gur->svr); 147 major = SVR_MAJ(svr); 148 149 return major; 150 } 151 152 void ddrmc_init(void) 153 { 154 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 155 u32 temp_sdram_cfg; 156 157 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 158 159 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 160 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 161 162 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 163 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 164 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 165 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 166 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 167 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 168 169 #ifdef CONFIG_DEEP_SLEEP 170 if (is_warm_boot()) { 171 out_be32(&ddr->sdram_cfg_2, 172 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); 173 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 174 out_be32(&ddr->init_ext_addr, (1 << 31)); 175 176 /* DRAM VRef will not be trained */ 177 out_be32(&ddr->ddr_cdr2, 178 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); 179 } else 180 #endif 181 { 182 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 183 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 184 } 185 186 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 187 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 188 189 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 190 191 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 192 193 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 194 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 195 196 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 197 198 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 199 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 200 201 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 202 udelay(1); 203 204 #ifdef CONFIG_DEEP_SLEEP 205 if (is_warm_boot()) { 206 /* enter self-refresh */ 207 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 208 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 209 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 210 211 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); 212 } else 213 #endif 214 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 215 216 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 217 218 #ifdef CONFIG_DEEP_SLEEP 219 if (is_warm_boot()) { 220 /* exit self-refresh */ 221 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 222 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 223 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 224 } 225 #endif 226 } 227 228 int dram_init(void) 229 { 230 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 231 ddrmc_init(); 232 #endif 233 234 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 235 236 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 237 fsl_dp_resume(); 238 #endif 239 240 return 0; 241 } 242 243 #ifdef CONFIG_FSL_ESDHC 244 struct fsl_esdhc_cfg esdhc_cfg[1] = { 245 {CONFIG_SYS_FSL_ESDHC_ADDR}, 246 }; 247 248 int board_mmc_init(bd_t *bis) 249 { 250 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 251 252 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 253 } 254 #endif 255 256 #ifdef CONFIG_TSEC_ENET 257 int board_eth_init(bd_t *bis) 258 { 259 struct fsl_pq_mdio_info mdio_info; 260 struct tsec_info_struct tsec_info[4]; 261 int num = 0; 262 263 #ifdef CONFIG_TSEC1 264 SET_STD_TSEC_INFO(tsec_info[num], 1); 265 if (is_serdes_configured(SGMII_TSEC1)) { 266 puts("eTSEC1 is in sgmii mode.\n"); 267 tsec_info[num].flags |= TSEC_SGMII; 268 } 269 num++; 270 #endif 271 #ifdef CONFIG_TSEC2 272 SET_STD_TSEC_INFO(tsec_info[num], 2); 273 if (is_serdes_configured(SGMII_TSEC2)) { 274 puts("eTSEC2 is in sgmii mode.\n"); 275 tsec_info[num].flags |= TSEC_SGMII; 276 } 277 num++; 278 #endif 279 #ifdef CONFIG_TSEC3 280 SET_STD_TSEC_INFO(tsec_info[num], 3); 281 num++; 282 #endif 283 if (!num) { 284 printf("No TSECs initialized\n"); 285 return 0; 286 } 287 288 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 289 mdio_info.name = DEFAULT_MII_NAME; 290 fsl_pq_mdio_init(bis, &mdio_info); 291 292 tsec_eth_init(bis, tsec_info, num); 293 294 return pci_eth_init(bis); 295 } 296 #endif 297 298 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 299 int config_serdes_mux(void) 300 { 301 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 302 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 303 304 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 305 switch (protocol) { 306 case 0x10: 307 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 308 convert_serdes_mux(LANED_PCIEX2 | 309 LANEC_PCIEX1, KEEP_STATUS); 310 break; 311 case 0x20: 312 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 313 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 314 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 315 break; 316 case 0x30: 317 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 318 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 319 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 320 break; 321 case 0x70: 322 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 323 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 324 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 325 break; 326 } 327 328 return 0; 329 } 330 #endif 331 332 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 333 int config_board_mux(void) 334 { 335 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 336 int conflict_flag; 337 338 conflict_flag = 0; 339 if (hwconfig("i2c3")) { 340 conflict_flag++; 341 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 342 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; 343 } 344 345 if (hwconfig("ifc")) { 346 conflict_flag++; 347 /* some signals can not enable simultaneous*/ 348 if (conflict_flag > 1) 349 goto conflict; 350 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 351 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; 352 } 353 354 conflict_flag = 0; 355 if (hwconfig("usb2")) { 356 conflict_flag++; 357 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 358 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; 359 } 360 361 if (hwconfig("can3")) { 362 conflict_flag++; 363 /* some signals can not enable simultaneous*/ 364 if (conflict_flag > 1) 365 goto conflict; 366 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 367 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; 368 } 369 370 conflict_flag = 0; 371 if (hwconfig("lcd")) { 372 conflict_flag++; 373 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 374 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; 375 } 376 377 if (hwconfig("qe")) { 378 conflict_flag++; 379 /* some signals can not enable simultaneous*/ 380 if (conflict_flag > 1) 381 goto conflict; 382 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 383 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; 384 } 385 386 return 0; 387 388 conflict: 389 printf("WARNING: pin conflict! MUX setting may failed!\n"); 390 return 0; 391 } 392 #endif 393 394 int board_early_init_f(void) 395 { 396 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 397 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 398 unsigned int major; 399 400 #ifdef CONFIG_TSEC_ENET 401 /* clear BD & FR bits for BE BD's and frame data */ 402 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 403 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 404 #endif 405 406 #ifdef CONFIG_FSL_IFC 407 init_early_memctl_regs(); 408 #endif 409 410 #ifdef CONFIG_FSL_DCU_FB 411 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 412 #endif 413 414 #ifdef CONFIG_FSL_QSPI 415 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 416 #endif 417 418 /* Configure Little endian for SAI, ASRC and SPDIF */ 419 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 420 421 /* 422 * Enable snoop requests and DVM message requests for 423 * Slave insterface S4 (A7 core cluster) 424 */ 425 out_le32(&cci->slave[4].snoop_ctrl, 426 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 427 428 major = get_soc_major_rev(); 429 if (major == SOC_MAJOR_VER_1_0) { 430 /* 431 * Set CCI-400 Slave interface S1, S2 Shareable Override 432 * Register All transactions are treated as non-shareable 433 */ 434 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 435 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 436 } 437 438 #if defined(CONFIG_DEEP_SLEEP) 439 if (is_warm_boot()) { 440 timer_init(); 441 dram_init(); 442 } 443 #endif 444 445 return 0; 446 } 447 448 #ifdef CONFIG_SPL_BUILD 449 void board_init_f(ulong dummy) 450 { 451 void (*second_uboot)(void); 452 453 /* Clear the BSS */ 454 memset(__bss_start, 0, __bss_end - __bss_start); 455 456 get_clocks(); 457 458 #if defined(CONFIG_DEEP_SLEEP) 459 if (is_warm_boot()) 460 fsl_dp_disable_console(); 461 #endif 462 463 preloader_console_init(); 464 465 dram_init(); 466 467 /* Allow OCRAM access permission as R/W */ 468 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 469 enable_layerscape_ns_access(); 470 enable_layerscape_ns_access(); 471 #endif 472 473 /* 474 * if it is woken up from deep sleep, then jump to second 475 * stage uboot and continue executing without recopying 476 * it from SD since it has already been reserved in memeory 477 * in last boot. 478 */ 479 if (is_warm_boot()) { 480 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; 481 second_uboot(); 482 } 483 484 board_init_r(NULL, 0); 485 } 486 #endif 487 488 489 struct liodn_id_table sec_liodn_tbl[] = { 490 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 491 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 492 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 493 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 494 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 495 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 496 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 497 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 498 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 499 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 500 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 501 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 502 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 503 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 504 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 505 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 506 }; 507 508 struct smmu_stream_id dev_stream_id[] = { 509 { 0x100, 0x01, "ETSEC MAC1" }, 510 { 0x104, 0x02, "ETSEC MAC2" }, 511 { 0x108, 0x03, "ETSEC MAC3" }, 512 { 0x10c, 0x04, "PEX1" }, 513 { 0x110, 0x05, "PEX2" }, 514 { 0x114, 0x06, "qDMA" }, 515 { 0x118, 0x07, "SATA" }, 516 { 0x11c, 0x08, "USB3" }, 517 { 0x120, 0x09, "QE" }, 518 { 0x124, 0x0a, "eSDHC" }, 519 { 0x128, 0x0b, "eMA" }, 520 { 0x14c, 0x0c, "2D-ACE" }, 521 { 0x150, 0x0d, "USB2" }, 522 { 0x18c, 0x0e, "DEBUG" }, 523 }; 524 525 #ifdef CONFIG_DEEP_SLEEP 526 /* program the regulator (MC34VR500) to support deep sleep */ 527 void ls1twr_program_regulator(void) 528 { 529 unsigned int i2c_bus; 530 u8 i2c_device_id; 531 532 #define LS1TWR_I2C_BUS_MC34VR500 1 533 #define MC34VR500_ADDR 0x8 534 #define MC34VR500_DEVICEID 0x4 535 #define MC34VR500_DEVICEID_MASK 0x0f 536 537 i2c_bus = i2c_get_bus_num(); 538 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); 539 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & 540 MC34VR500_DEVICEID_MASK; 541 if (i2c_device_id != MC34VR500_DEVICEID) { 542 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); 543 return; 544 } 545 546 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); 547 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); 548 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); 549 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); 550 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); 551 552 i2c_set_bus_num(i2c_bus); 553 } 554 #endif 555 556 int board_init(void) 557 { 558 #ifndef CONFIG_SYS_FSL_NO_SERDES 559 fsl_serdes_init(); 560 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 561 config_serdes_mux(); 562 #endif 563 #endif 564 565 ls1021x_config_caam_stream_id(sec_liodn_tbl, 566 ARRAY_SIZE(sec_liodn_tbl)); 567 ls102xa_config_smmu_stream_id(dev_stream_id, 568 ARRAY_SIZE(dev_stream_id)); 569 570 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 571 enable_layerscape_ns_access(); 572 #endif 573 574 #ifdef CONFIG_U_QE 575 u_qe_init(); 576 #endif 577 578 #ifdef CONFIG_DEEP_SLEEP 579 ls1twr_program_regulator(); 580 #endif 581 return 0; 582 } 583 584 #ifdef CONFIG_BOARD_LATE_INIT 585 int board_late_init(void) 586 { 587 #ifdef CONFIG_SCSI_AHCI_PLAT 588 ls1021a_sata_init(); 589 #endif 590 591 return 0; 592 } 593 #endif 594 595 #if defined(CONFIG_MISC_INIT_R) 596 int misc_init_r(void) 597 { 598 #ifdef CONFIG_FSL_DEVICE_DISABLE 599 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 600 #endif 601 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 602 config_board_mux(); 603 #endif 604 605 #ifdef CONFIG_FSL_CAAM 606 return sec_init(); 607 #endif 608 } 609 #endif 610 611 #if defined(CONFIG_DEEP_SLEEP) 612 void board_sleep_prepare(void) 613 { 614 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 615 enable_layerscape_ns_access(); 616 #endif 617 } 618 #endif 619 620 int ft_board_setup(void *blob, bd_t *bd) 621 { 622 ft_cpu_setup(blob, bd); 623 624 #ifdef CONFIG_PCI 625 ft_pci_setup(blob, bd); 626 #endif 627 628 return 0; 629 } 630 631 u8 flash_read8(void *addr) 632 { 633 return __raw_readb(addr + 1); 634 } 635 636 void flash_write16(u16 val, void *addr) 637 { 638 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 639 640 __raw_writew(shftval, addr); 641 } 642 643 u16 flash_read16(void *addr) 644 { 645 u16 val = __raw_readw(addr); 646 647 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 648 } 649 650 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 651 static void convert_flash_bank(char bank) 652 { 653 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 654 655 printf("Now switch to boot from flash bank %d.\n", bank); 656 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 657 cpld_data->vbank = bank; 658 659 printf("Reset board to enable configuration.\n"); 660 cpld_data->system_rst = CONFIG_RESET; 661 } 662 663 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 664 char * const argv[]) 665 { 666 if (argc != 2) 667 return CMD_RET_USAGE; 668 if (strcmp(argv[1], "0") == 0) 669 convert_flash_bank(BOOT_FROM_UPPER_BANK); 670 else if (strcmp(argv[1], "1") == 0) 671 convert_flash_bank(BOOT_FROM_LOWER_BANK); 672 else 673 return CMD_RET_USAGE; 674 675 return 0; 676 } 677 678 U_BOOT_CMD( 679 boot_bank, 2, 0, flash_bank_cmd, 680 "Flash bank Selection Control", 681 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 682 ); 683 684 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 685 char * const argv[]) 686 { 687 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 688 689 if (argc > 2) 690 return CMD_RET_USAGE; 691 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 692 cpld_data->system_rst = CONFIG_RESET; 693 else if (strcmp(argv[1], "init") == 0) 694 cpld_data->global_rst = INIT_RESET; 695 else 696 return CMD_RET_USAGE; 697 698 return 0; 699 } 700 701 U_BOOT_CMD( 702 cpld_reset, 2, 0, cpld_reset_cmd, 703 "Reset via CPLD", 704 "conf\n" 705 " -reset with current CPLD configuration\n" 706 "init\n" 707 " -reset and initial CPLD configuration with default value" 708 709 ); 710 711 static void convert_serdes_mux(int type, int need_reset) 712 { 713 char current_serdes; 714 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 715 716 current_serdes = cpld_data->serdes_mux; 717 718 switch (type) { 719 case LANEB_SATA: 720 current_serdes &= ~MASK_LANE_B; 721 break; 722 case LANEB_SGMII1: 723 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 724 break; 725 case LANEC_SGMII1: 726 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 727 break; 728 case LANED_SGMII2: 729 current_serdes |= MASK_LANE_D; 730 break; 731 case LANEC_PCIEX1: 732 current_serdes |= MASK_LANE_C; 733 break; 734 case (LANED_PCIEX2 | LANEC_PCIEX1): 735 current_serdes |= MASK_LANE_C; 736 current_serdes &= ~MASK_LANE_D; 737 break; 738 default: 739 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 740 return; 741 } 742 743 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 744 cpld_data->serdes_mux = current_serdes; 745 746 if (need_reset == 1) { 747 printf("Reset board to enable configuration\n"); 748 cpld_data->system_rst = CONFIG_RESET; 749 } 750 } 751 752 void print_serdes_mux(void) 753 { 754 char current_serdes; 755 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 756 757 current_serdes = cpld_data->serdes_mux; 758 759 printf("Serdes Lane B: "); 760 if ((current_serdes & MASK_LANE_B) == 0) 761 printf("SATA,\n"); 762 else 763 printf("SGMII 1,\n"); 764 765 printf("Serdes Lane C: "); 766 if ((current_serdes & MASK_LANE_C) == 0) 767 printf("SGMII 1,\n"); 768 else 769 printf("PCIe,\n"); 770 771 printf("Serdes Lane D: "); 772 if ((current_serdes & MASK_LANE_D) == 0) 773 printf("PCIe,\n"); 774 else 775 printf("SGMII 2,\n"); 776 777 printf("SGMII 1 is on lane "); 778 if ((current_serdes & MASK_SGMII) == 0) 779 printf("C.\n"); 780 else 781 printf("B.\n"); 782 } 783 784 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 785 char * const argv[]) 786 { 787 if (argc != 2) 788 return CMD_RET_USAGE; 789 if (strcmp(argv[1], "sata") == 0) { 790 printf("Set serdes lane B to SATA.\n"); 791 convert_serdes_mux(LANEB_SATA, NEED_RESET); 792 } else if (strcmp(argv[1], "sgmii1b") == 0) { 793 printf("Set serdes lane B to SGMII 1.\n"); 794 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 795 } else if (strcmp(argv[1], "sgmii1c") == 0) { 796 printf("Set serdes lane C to SGMII 1.\n"); 797 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 798 } else if (strcmp(argv[1], "sgmii2") == 0) { 799 printf("Set serdes lane D to SGMII 2.\n"); 800 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 801 } else if (strcmp(argv[1], "pciex1") == 0) { 802 printf("Set serdes lane C to PCIe X1.\n"); 803 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 804 } else if (strcmp(argv[1], "pciex2") == 0) { 805 printf("Set serdes lane C & lane D to PCIe X2.\n"); 806 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 807 } else if (strcmp(argv[1], "show") == 0) { 808 print_serdes_mux(); 809 } else { 810 return CMD_RET_USAGE; 811 } 812 813 return 0; 814 } 815 816 U_BOOT_CMD( 817 lane_bank, 2, 0, serdes_mux_cmd, 818 "Multiplexed function setting for SerDes Lanes", 819 "sata\n" 820 " -change lane B to sata\n" 821 "lane_bank sgmii1b\n" 822 " -change lane B to SGMII1\n" 823 "lane_bank sgmii1c\n" 824 " -change lane C to SGMII1\n" 825 "lane_bank sgmii2\n" 826 " -change lane D to SGMII2\n" 827 "lane_bank pciex1\n" 828 " -change lane C to PCIeX1\n" 829 "lane_bank pciex2\n" 830 " -change lane C & lane D to PCIeX2\n" 831 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 832 ); 833 #endif 834