1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <fsl_ifc.h>
16 #include <netdev.h>
17 #include <fsl_mdio.h>
18 #include <tsec.h>
19 #include <fsl_sec.h>
20 #ifdef CONFIG_U_QE
21 #include "../../../drivers/qe/qe.h"
22 #endif
23 
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 #define VERSION_MASK		0x00FF
28 #define BANK_MASK		0x0001
29 #define CONFIG_RESET		0x1
30 #define INIT_RESET		0x1
31 
32 #define CPLD_SET_MUX_SERDES	0x20
33 #define CPLD_SET_BOOT_BANK	0x40
34 
35 #define BOOT_FROM_UPPER_BANK	0x0
36 #define BOOT_FROM_LOWER_BANK	0x1
37 
38 #define LANEB_SATA		(0x01)
39 #define LANEB_SGMII1		(0x02)
40 #define LANEC_SGMII1		(0x04)
41 #define LANEC_PCIEX1		(0x08)
42 #define LANED_PCIEX2		(0x10)
43 #define LANED_SGMII2		(0x20)
44 
45 #define MASK_LANE_B		0x1
46 #define MASK_LANE_C		0x2
47 #define MASK_LANE_D		0x4
48 #define MASK_SGMII		0x8
49 
50 #define KEEP_STATUS		0x0
51 #define NEED_RESET		0x1
52 
53 struct cpld_data {
54 	u8 cpld_ver;		/* cpld revision */
55 	u8 cpld_ver_sub;	/* cpld sub revision */
56 	u8 pcba_ver;		/* pcb revision number */
57 	u8 system_rst;		/* reset system by cpld */
58 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
59 	u8 cfg_rcw_src1;	/* Reset config word 1 */
60 	u8 cfg_rcw_src2;	/* Reset config word 2 */
61 	u8 vbank;		/* Flash bank selection Control */
62 	u8 gpio;		/* GPIO for TWR-ELEV */
63 	u8 i2c3_ifc_mux;
64 	u8 mux_spi2;
65 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
66 	u8 qe_lcd_mux;		/* QE and LCD Selection */
67 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
68 	u8 global_rst;		/* reset with init CPLD reg to default */
69 	u8 rev1;		/* Reserved */
70 	u8 rev2;		/* Reserved */
71 };
72 
73 static void convert_serdes_mux(int type, int need_reset);
74 
75 void cpld_show(void)
76 {
77 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
78 
79 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
80 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
81 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
82 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
83 	       in_8(&cpld_data->vbank) & BANK_MASK);
84 
85 #ifdef CONFIG_DEBUG
86 	printf("soft_mux_on =%x\n",
87 	       in_8(&cpld_data->soft_mux_on));
88 	printf("cfg_rcw_src1 =%x\n",
89 	       in_8(&cpld_data->cfg_rcw_src1));
90 	printf("cfg_rcw_src2 =%x\n",
91 	       in_8(&cpld_data->cfg_rcw_src2));
92 	printf("vbank =%x\n",
93 	       in_8(&cpld_data->vbank));
94 	printf("gpio =%x\n",
95 	       in_8(&cpld_data->gpio));
96 	printf("i2c3_ifc_mux =%x\n",
97 	       in_8(&cpld_data->i2c3_ifc_mux));
98 	printf("mux_spi2 =%x\n",
99 	       in_8(&cpld_data->mux_spi2));
100 	printf("can3_usb2_mux =%x\n",
101 	       in_8(&cpld_data->can3_usb2_mux));
102 	printf("qe_lcd_mux =%x\n",
103 	       in_8(&cpld_data->qe_lcd_mux));
104 	printf("serdes_mux =%x\n",
105 	       in_8(&cpld_data->serdes_mux));
106 #endif
107 }
108 
109 int checkboard(void)
110 {
111 	puts("Board: LS1021ATWR\n");
112 	cpld_show();
113 
114 	return 0;
115 }
116 
117 void ddrmc_init(void)
118 {
119 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
120 
121 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
122 
123 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
124 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
125 
126 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
127 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
128 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
129 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
130 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
131 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
132 
133 	out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
134 
135 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
136 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
137 
138 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
139 
140 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
141 
142 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
143 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
144 
145 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
146 	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
147 
148 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
149 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
150 
151 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
152 	udelay(1);
153 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
154 }
155 
156 int dram_init(void)
157 {
158 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
159 	ddrmc_init();
160 #endif
161 
162 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
163 	return 0;
164 }
165 
166 #ifdef CONFIG_FSL_ESDHC
167 struct fsl_esdhc_cfg esdhc_cfg[1] = {
168 	{CONFIG_SYS_FSL_ESDHC_ADDR},
169 };
170 
171 int board_mmc_init(bd_t *bis)
172 {
173 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
174 
175 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
176 }
177 #endif
178 
179 #ifdef CONFIG_TSEC_ENET
180 int board_eth_init(bd_t *bis)
181 {
182 	struct fsl_pq_mdio_info mdio_info;
183 	struct tsec_info_struct tsec_info[4];
184 	int num = 0;
185 
186 #ifdef CONFIG_TSEC1
187 	SET_STD_TSEC_INFO(tsec_info[num], 1);
188 	if (is_serdes_configured(SGMII_TSEC1)) {
189 		puts("eTSEC1 is in sgmii mode.\n");
190 		tsec_info[num].flags |= TSEC_SGMII;
191 	}
192 	num++;
193 #endif
194 #ifdef CONFIG_TSEC2
195 	SET_STD_TSEC_INFO(tsec_info[num], 2);
196 	if (is_serdes_configured(SGMII_TSEC2)) {
197 		puts("eTSEC2 is in sgmii mode.\n");
198 		tsec_info[num].flags |= TSEC_SGMII;
199 	}
200 	num++;
201 #endif
202 #ifdef CONFIG_TSEC3
203 	SET_STD_TSEC_INFO(tsec_info[num], 3);
204 	num++;
205 #endif
206 	if (!num) {
207 		printf("No TSECs initialized\n");
208 		return 0;
209 	}
210 
211 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
212 	mdio_info.name = DEFAULT_MII_NAME;
213 	fsl_pq_mdio_init(bis, &mdio_info);
214 
215 	tsec_eth_init(bis, tsec_info, num);
216 
217 	return pci_eth_init(bis);
218 }
219 #endif
220 
221 int config_serdes_mux(void)
222 {
223 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
224 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
225 
226 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
227 	switch (protocol) {
228 	case 0x10:
229 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
230 		convert_serdes_mux(LANED_PCIEX2 |
231 				LANEC_PCIEX1, KEEP_STATUS);
232 		break;
233 	case 0x20:
234 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
235 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
236 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
237 		break;
238 	case 0x30:
239 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
240 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
241 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
242 		break;
243 	case 0x70:
244 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
245 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
246 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
247 		break;
248 	}
249 
250 	return 0;
251 }
252 
253 int board_early_init_f(void)
254 {
255 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
256 
257 #ifdef CONFIG_TSEC_ENET
258 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
259 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
260 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
261 	udelay(10);
262 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
263 #endif
264 
265 #ifdef CONFIG_FSL_IFC
266 	init_early_memctl_regs();
267 #endif
268 
269 #ifdef CONFIG_FSL_DCU_FB
270 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
271 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
272 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
273 #endif
274 
275 	return 0;
276 }
277 
278 int board_init(void)
279 {
280 #ifndef CONFIG_SYS_FSL_NO_SERDES
281 	fsl_serdes_init();
282 	config_serdes_mux();
283 #endif
284 
285 #ifdef CONFIG_U_QE
286 	u_qe_init();
287 #endif
288 
289 	return 0;
290 }
291 
292 #if defined(CONFIG_MISC_INIT_R)
293 int misc_init_r(void)
294 {
295 #ifdef CONFIG_FSL_CAAM
296 	return sec_init();
297 #endif
298 }
299 #endif
300 
301 void ft_board_setup(void *blob, bd_t *bd)
302 {
303 	ft_cpu_setup(blob, bd);
304 }
305 
306 u8 flash_read8(void *addr)
307 {
308 	return __raw_readb(addr + 1);
309 }
310 
311 void flash_write16(u16 val, void *addr)
312 {
313 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
314 
315 	__raw_writew(shftval, addr);
316 }
317 
318 u16 flash_read16(void *addr)
319 {
320 	u16 val = __raw_readw(addr);
321 
322 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
323 }
324 
325 static void convert_flash_bank(char bank)
326 {
327 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
328 
329 	printf("Now switch to boot from flash bank %d.\n", bank);
330 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
331 	cpld_data->vbank = bank;
332 
333 	printf("Reset board to enable configuration.\n");
334 	cpld_data->system_rst = CONFIG_RESET;
335 }
336 
337 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
338 			  char * const argv[])
339 {
340 	if (argc != 2)
341 		return CMD_RET_USAGE;
342 	if (strcmp(argv[1], "0") == 0)
343 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
344 	else if (strcmp(argv[1], "1") == 0)
345 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
346 	else
347 		return CMD_RET_USAGE;
348 
349 	return 0;
350 }
351 
352 U_BOOT_CMD(
353 	boot_bank, 2, 0, flash_bank_cmd,
354 	"Flash bank Selection Control",
355 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
356 );
357 
358 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
359 			  char * const argv[])
360 {
361 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
362 
363 	if (argc > 2)
364 		return CMD_RET_USAGE;
365 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
366 		cpld_data->system_rst = CONFIG_RESET;
367 	else if (strcmp(argv[1], "init") == 0)
368 		cpld_data->global_rst = INIT_RESET;
369 	else
370 		return CMD_RET_USAGE;
371 
372 	return 0;
373 }
374 
375 U_BOOT_CMD(
376 	cpld_reset, 2, 0, cpld_reset_cmd,
377 	"Reset via CPLD",
378 	"conf\n"
379 	"	-reset with current CPLD configuration\n"
380 	"init\n"
381 	"	-reset and initial CPLD configuration with default value"
382 
383 );
384 
385 static void convert_serdes_mux(int type, int need_reset)
386 {
387 	char current_serdes;
388 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
389 
390 	current_serdes = cpld_data->serdes_mux;
391 
392 	switch (type) {
393 	case LANEB_SATA:
394 		current_serdes &= ~MASK_LANE_B;
395 		break;
396 	case LANEB_SGMII1:
397 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
398 		break;
399 	case LANEC_SGMII1:
400 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
401 		break;
402 	case LANED_SGMII2:
403 		current_serdes |= MASK_LANE_D;
404 		break;
405 	case LANEC_PCIEX1:
406 		current_serdes |= MASK_LANE_C;
407 		break;
408 	case (LANED_PCIEX2 | LANEC_PCIEX1):
409 		current_serdes |= MASK_LANE_C;
410 		current_serdes &= ~MASK_LANE_D;
411 		break;
412 	default:
413 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
414 		return;
415 	}
416 
417 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
418 	cpld_data->serdes_mux = current_serdes;
419 
420 	if (need_reset == 1) {
421 		printf("Reset board to enable configuration\n");
422 		cpld_data->system_rst = CONFIG_RESET;
423 	}
424 }
425 
426 void print_serdes_mux(void)
427 {
428 	char current_serdes;
429 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
430 
431 	current_serdes = cpld_data->serdes_mux;
432 
433 	printf("Serdes Lane B: ");
434 	if ((current_serdes & MASK_LANE_B) == 0)
435 		printf("SATA,\n");
436 	else
437 		printf("SGMII 1,\n");
438 
439 	printf("Serdes Lane C: ");
440 	if ((current_serdes & MASK_LANE_C) == 0)
441 		printf("SGMII 1,\n");
442 	else
443 		printf("PCIe,\n");
444 
445 	printf("Serdes Lane D: ");
446 	if ((current_serdes & MASK_LANE_D) == 0)
447 		printf("PCIe,\n");
448 	else
449 		printf("SGMII 2,\n");
450 
451 	printf("SGMII 1 is on lane ");
452 	if ((current_serdes & MASK_SGMII) == 0)
453 		printf("C.\n");
454 	else
455 		printf("B.\n");
456 }
457 
458 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
459 			  char * const argv[])
460 {
461 	if (argc != 2)
462 		return CMD_RET_USAGE;
463 	if (strcmp(argv[1], "sata") == 0) {
464 		printf("Set serdes lane B to SATA.\n");
465 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
466 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
467 		printf("Set serdes lane B to SGMII 1.\n");
468 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
469 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
470 		printf("Set serdes lane C to SGMII 1.\n");
471 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
472 	} else if (strcmp(argv[1], "sgmii2") == 0) {
473 		printf("Set serdes lane D to SGMII 2.\n");
474 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
475 	} else if (strcmp(argv[1], "pciex1") == 0) {
476 		printf("Set serdes lane C to PCIe X1.\n");
477 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
478 	} else if (strcmp(argv[1], "pciex2") == 0) {
479 		printf("Set serdes lane C & lane D to PCIe X2.\n");
480 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
481 	} else if (strcmp(argv[1], "show") == 0) {
482 		print_serdes_mux();
483 	} else {
484 		return CMD_RET_USAGE;
485 	}
486 
487 	return 0;
488 }
489 
490 U_BOOT_CMD(
491 	lane_bank, 2, 0, serdes_mux_cmd,
492 	"Multiplexed function setting for SerDes Lanes",
493 	"sata\n"
494 	"	-change lane B to sata\n"
495 	"lane_bank sgmii1b\n"
496 	"	-change lane B to SGMII1\n"
497 	"lane_bank sgmii1c\n"
498 	"	-change lane C to SGMII1\n"
499 	"lane_bank sgmii2\n"
500 	"	-change lane D to SGMII2\n"
501 	"lane_bank pciex1\n"
502 	"	-change lane C to PCIeX1\n"
503 	"lane_bank pciex2\n"
504 	"	-change lane C & lane D to PCIeX2\n"
505 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
506 );
507