1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <fsl_ifc.h>
16 #include <netdev.h>
17 #include <fsl_mdio.h>
18 #include <tsec.h>
19 #include <fsl_sec.h>
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 #define VERSION_MASK		0x00FF
24 #define BANK_MASK		0x0001
25 #define CONFIG_RESET		0x1
26 #define INIT_RESET		0x1
27 
28 #define CPLD_SET_MUX_SERDES	0x20
29 #define CPLD_SET_BOOT_BANK	0x40
30 
31 #define BOOT_FROM_UPPER_BANK	0x0
32 #define BOOT_FROM_LOWER_BANK	0x1
33 
34 #define LANEB_SATA		(0x01)
35 #define LANEB_SGMII1		(0x02)
36 #define LANEC_SGMII1		(0x04)
37 #define LANEC_PCIEX1		(0x08)
38 #define LANED_PCIEX2		(0x10)
39 #define LANED_SGMII2		(0x20)
40 
41 #define MASK_LANE_B		0x1
42 #define MASK_LANE_C		0x2
43 #define MASK_LANE_D		0x4
44 #define MASK_SGMII		0x8
45 
46 #define KEEP_STATUS		0x0
47 #define NEED_RESET		0x1
48 
49 struct cpld_data {
50 	u8 cpld_ver;		/* cpld revision */
51 	u8 cpld_ver_sub;	/* cpld sub revision */
52 	u8 pcba_ver;		/* pcb revision number */
53 	u8 system_rst;		/* reset system by cpld */
54 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
55 	u8 cfg_rcw_src1;	/* Reset config word 1 */
56 	u8 cfg_rcw_src2;	/* Reset config word 2 */
57 	u8 vbank;		/* Flash bank selection Control */
58 	u8 gpio;		/* GPIO for TWR-ELEV */
59 	u8 i2c3_ifc_mux;
60 	u8 mux_spi2;
61 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
62 	u8 qe_lcd_mux;		/* QE and LCD Selection */
63 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
64 	u8 global_rst;		/* reset with init CPLD reg to default */
65 	u8 rev1;		/* Reserved */
66 	u8 rev2;		/* Reserved */
67 };
68 
69 static void convert_serdes_mux(int type, int need_reset);
70 
71 void cpld_show(void)
72 {
73 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
74 
75 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
76 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
77 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
78 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
79 	       in_8(&cpld_data->vbank) & BANK_MASK);
80 
81 #ifdef CONFIG_DEBUG
82 	printf("soft_mux_on =%x\n",
83 	       in_8(&cpld_data->soft_mux_on));
84 	printf("cfg_rcw_src1 =%x\n",
85 	       in_8(&cpld_data->cfg_rcw_src1));
86 	printf("cfg_rcw_src2 =%x\n",
87 	       in_8(&cpld_data->cfg_rcw_src2));
88 	printf("vbank =%x\n",
89 	       in_8(&cpld_data->vbank));
90 	printf("gpio =%x\n",
91 	       in_8(&cpld_data->gpio));
92 	printf("i2c3_ifc_mux =%x\n",
93 	       in_8(&cpld_data->i2c3_ifc_mux));
94 	printf("mux_spi2 =%x\n",
95 	       in_8(&cpld_data->mux_spi2));
96 	printf("can3_usb2_mux =%x\n",
97 	       in_8(&cpld_data->can3_usb2_mux));
98 	printf("qe_lcd_mux =%x\n",
99 	       in_8(&cpld_data->qe_lcd_mux));
100 	printf("serdes_mux =%x\n",
101 	       in_8(&cpld_data->serdes_mux));
102 #endif
103 }
104 
105 int checkboard(void)
106 {
107 	puts("Board: LS1021ATWR\n");
108 	cpld_show();
109 
110 	return 0;
111 }
112 
113 void ddrmc_init(void)
114 {
115 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
116 
117 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
118 
119 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
120 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
121 
122 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
123 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
124 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
125 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
126 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
127 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
128 
129 	out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
130 
131 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
132 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
133 
134 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
135 
136 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
137 
138 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
139 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
140 
141 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
142 	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
143 
144 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
145 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
146 
147 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
148 	udelay(1);
149 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
150 }
151 
152 int dram_init(void)
153 {
154 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
155 	ddrmc_init();
156 #endif
157 
158 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
159 	return 0;
160 }
161 
162 #ifdef CONFIG_FSL_ESDHC
163 struct fsl_esdhc_cfg esdhc_cfg[1] = {
164 	{CONFIG_SYS_FSL_ESDHC_ADDR},
165 };
166 
167 int board_mmc_init(bd_t *bis)
168 {
169 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
170 
171 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
172 }
173 #endif
174 
175 #ifdef CONFIG_TSEC_ENET
176 int board_eth_init(bd_t *bis)
177 {
178 	struct fsl_pq_mdio_info mdio_info;
179 	struct tsec_info_struct tsec_info[4];
180 	int num = 0;
181 
182 #ifdef CONFIG_TSEC1
183 	SET_STD_TSEC_INFO(tsec_info[num], 1);
184 	if (is_serdes_configured(SGMII_TSEC1)) {
185 		puts("eTSEC1 is in sgmii mode.\n");
186 		tsec_info[num].flags |= TSEC_SGMII;
187 	}
188 	num++;
189 #endif
190 #ifdef CONFIG_TSEC2
191 	SET_STD_TSEC_INFO(tsec_info[num], 2);
192 	if (is_serdes_configured(SGMII_TSEC2)) {
193 		puts("eTSEC2 is in sgmii mode.\n");
194 		tsec_info[num].flags |= TSEC_SGMII;
195 	}
196 	num++;
197 #endif
198 #ifdef CONFIG_TSEC3
199 	SET_STD_TSEC_INFO(tsec_info[num], 3);
200 	num++;
201 #endif
202 	if (!num) {
203 		printf("No TSECs initialized\n");
204 		return 0;
205 	}
206 
207 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
208 	mdio_info.name = DEFAULT_MII_NAME;
209 	fsl_pq_mdio_init(bis, &mdio_info);
210 
211 	tsec_eth_init(bis, tsec_info, num);
212 
213 	return pci_eth_init(bis);
214 }
215 #endif
216 
217 int config_serdes_mux(void)
218 {
219 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
220 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
221 
222 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
223 	switch (protocol) {
224 	case 0x10:
225 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
226 		convert_serdes_mux(LANED_PCIEX2 |
227 				LANEC_PCIEX1, KEEP_STATUS);
228 		break;
229 	case 0x20:
230 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
231 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
232 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
233 		break;
234 	case 0x30:
235 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
236 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
237 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
238 		break;
239 	case 0x70:
240 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
241 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
242 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
243 		break;
244 	}
245 
246 	return 0;
247 }
248 
249 int board_early_init_f(void)
250 {
251 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
252 
253 #ifdef CONFIG_TSEC_ENET
254 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
255 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
256 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
257 	udelay(10);
258 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
259 #endif
260 
261 #ifdef CONFIG_FSL_IFC
262 	init_early_memctl_regs();
263 #endif
264 
265 #ifdef CONFIG_FSL_DCU_FB
266 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
267 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
268 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
269 #endif
270 
271 	return 0;
272 }
273 
274 int board_init(void)
275 {
276 #ifndef CONFIG_SYS_FSL_NO_SERDES
277 	fsl_serdes_init();
278 	config_serdes_mux();
279 #endif
280 
281 	return 0;
282 }
283 
284 #if defined(CONFIG_MISC_INIT_R)
285 int misc_init_r(void)
286 {
287 #ifdef CONFIG_FSL_CAAM
288 	return sec_init();
289 #endif
290 }
291 #endif
292 
293 void ft_board_setup(void *blob, bd_t *bd)
294 {
295 	ft_cpu_setup(blob, bd);
296 }
297 
298 u8 flash_read8(void *addr)
299 {
300 	return __raw_readb(addr + 1);
301 }
302 
303 void flash_write16(u16 val, void *addr)
304 {
305 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
306 
307 	__raw_writew(shftval, addr);
308 }
309 
310 u16 flash_read16(void *addr)
311 {
312 	u16 val = __raw_readw(addr);
313 
314 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
315 }
316 
317 static void convert_flash_bank(char bank)
318 {
319 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
320 
321 	printf("Now switch to boot from flash bank %d.\n", bank);
322 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
323 	cpld_data->vbank = bank;
324 
325 	printf("Reset board to enable configuration.\n");
326 	cpld_data->system_rst = CONFIG_RESET;
327 }
328 
329 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
330 			  char * const argv[])
331 {
332 	if (argc != 2)
333 		return CMD_RET_USAGE;
334 	if (strcmp(argv[1], "0") == 0)
335 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
336 	else if (strcmp(argv[1], "1") == 0)
337 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
338 	else
339 		return CMD_RET_USAGE;
340 
341 	return 0;
342 }
343 
344 U_BOOT_CMD(
345 	boot_bank, 2, 0, flash_bank_cmd,
346 	"Flash bank Selection Control",
347 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
348 );
349 
350 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
351 			  char * const argv[])
352 {
353 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
354 
355 	if (argc > 2)
356 		return CMD_RET_USAGE;
357 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
358 		cpld_data->system_rst = CONFIG_RESET;
359 	else if (strcmp(argv[1], "init") == 0)
360 		cpld_data->global_rst = INIT_RESET;
361 	else
362 		return CMD_RET_USAGE;
363 
364 	return 0;
365 }
366 
367 U_BOOT_CMD(
368 	cpld_reset, 2, 0, cpld_reset_cmd,
369 	"Reset via CPLD",
370 	"conf\n"
371 	"	-reset with current CPLD configuration\n"
372 	"init\n"
373 	"	-reset and initial CPLD configuration with default value"
374 
375 );
376 
377 static void convert_serdes_mux(int type, int need_reset)
378 {
379 	char current_serdes;
380 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
381 
382 	current_serdes = cpld_data->serdes_mux;
383 
384 	switch (type) {
385 	case LANEB_SATA:
386 		current_serdes &= ~MASK_LANE_B;
387 		break;
388 	case LANEB_SGMII1:
389 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
390 		break;
391 	case LANEC_SGMII1:
392 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
393 		break;
394 	case LANED_SGMII2:
395 		current_serdes |= MASK_LANE_D;
396 		break;
397 	case LANEC_PCIEX1:
398 		current_serdes |= MASK_LANE_C;
399 		break;
400 	case (LANED_PCIEX2 | LANEC_PCIEX1):
401 		current_serdes |= MASK_LANE_C;
402 		current_serdes &= ~MASK_LANE_D;
403 		break;
404 	default:
405 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
406 		return;
407 	}
408 
409 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
410 	cpld_data->serdes_mux = current_serdes;
411 
412 	if (need_reset == 1) {
413 		printf("Reset board to enable configuration\n");
414 		cpld_data->system_rst = CONFIG_RESET;
415 	}
416 }
417 
418 void print_serdes_mux(void)
419 {
420 	char current_serdes;
421 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
422 
423 	current_serdes = cpld_data->serdes_mux;
424 
425 	printf("Serdes Lane B: ");
426 	if ((current_serdes & MASK_LANE_B) == 0)
427 		printf("SATA,\n");
428 	else
429 		printf("SGMII 1,\n");
430 
431 	printf("Serdes Lane C: ");
432 	if ((current_serdes & MASK_LANE_C) == 0)
433 		printf("SGMII 1,\n");
434 	else
435 		printf("PCIe,\n");
436 
437 	printf("Serdes Lane D: ");
438 	if ((current_serdes & MASK_LANE_D) == 0)
439 		printf("PCIe,\n");
440 	else
441 		printf("SGMII 2,\n");
442 
443 	printf("SGMII 1 is on lane ");
444 	if ((current_serdes & MASK_SGMII) == 0)
445 		printf("C.\n");
446 	else
447 		printf("B.\n");
448 }
449 
450 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
451 			  char * const argv[])
452 {
453 	if (argc != 2)
454 		return CMD_RET_USAGE;
455 	if (strcmp(argv[1], "sata") == 0) {
456 		printf("Set serdes lane B to SATA.\n");
457 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
458 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
459 		printf("Set serdes lane B to SGMII 1.\n");
460 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
461 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
462 		printf("Set serdes lane C to SGMII 1.\n");
463 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
464 	} else if (strcmp(argv[1], "sgmii2") == 0) {
465 		printf("Set serdes lane D to SGMII 2.\n");
466 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
467 	} else if (strcmp(argv[1], "pciex1") == 0) {
468 		printf("Set serdes lane C to PCIe X1.\n");
469 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
470 	} else if (strcmp(argv[1], "pciex2") == 0) {
471 		printf("Set serdes lane C & lane D to PCIe X2.\n");
472 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
473 	} else if (strcmp(argv[1], "show") == 0) {
474 		print_serdes_mux();
475 	} else {
476 		return CMD_RET_USAGE;
477 	}
478 
479 	return 0;
480 }
481 
482 U_BOOT_CMD(
483 	lane_bank, 2, 0, serdes_mux_cmd,
484 	"Multiplexed function setting for SerDes Lanes",
485 	"sata\n"
486 	"	-change lane B to sata\n"
487 	"lane_bank sgmii1b\n"
488 	"	-change lane B to SGMII1\n"
489 	"lane_bank sgmii1c\n"
490 	"	-change lane C to SGMII1\n"
491 	"lane_bank sgmii2\n"
492 	"	-change lane D to SGMII2\n"
493 	"lane_bank pciex1\n"
494 	"	-change lane C to PCIeX1\n"
495 	"lane_bank pciex2\n"
496 	"	-change lane C & lane D to PCIeX2\n"
497 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
498 );
499