1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/pcie_layerscape.h> 14 #include <mmc.h> 15 #include <fsl_esdhc.h> 16 #include <fsl_ifc.h> 17 #include <netdev.h> 18 #include <fsl_mdio.h> 19 #include <tsec.h> 20 #include <fsl_sec.h> 21 #include <spl.h> 22 #ifdef CONFIG_U_QE 23 #include "../../../drivers/qe/qe.h" 24 #endif 25 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define VERSION_MASK 0x00FF 30 #define BANK_MASK 0x0001 31 #define CONFIG_RESET 0x1 32 #define INIT_RESET 0x1 33 34 #define CPLD_SET_MUX_SERDES 0x20 35 #define CPLD_SET_BOOT_BANK 0x40 36 37 #define BOOT_FROM_UPPER_BANK 0x0 38 #define BOOT_FROM_LOWER_BANK 0x1 39 40 #define LANEB_SATA (0x01) 41 #define LANEB_SGMII1 (0x02) 42 #define LANEC_SGMII1 (0x04) 43 #define LANEC_PCIEX1 (0x08) 44 #define LANED_PCIEX2 (0x10) 45 #define LANED_SGMII2 (0x20) 46 47 #define MASK_LANE_B 0x1 48 #define MASK_LANE_C 0x2 49 #define MASK_LANE_D 0x4 50 #define MASK_SGMII 0x8 51 52 #define KEEP_STATUS 0x0 53 #define NEED_RESET 0x1 54 55 struct cpld_data { 56 u8 cpld_ver; /* cpld revision */ 57 u8 cpld_ver_sub; /* cpld sub revision */ 58 u8 pcba_ver; /* pcb revision number */ 59 u8 system_rst; /* reset system by cpld */ 60 u8 soft_mux_on; /* CPLD override physical switches Enable */ 61 u8 cfg_rcw_src1; /* Reset config word 1 */ 62 u8 cfg_rcw_src2; /* Reset config word 2 */ 63 u8 vbank; /* Flash bank selection Control */ 64 u8 gpio; /* GPIO for TWR-ELEV */ 65 u8 i2c3_ifc_mux; 66 u8 mux_spi2; 67 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 68 u8 qe_lcd_mux; /* QE and LCD Selection */ 69 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 70 u8 global_rst; /* reset with init CPLD reg to default */ 71 u8 rev1; /* Reserved */ 72 u8 rev2; /* Reserved */ 73 }; 74 75 #ifndef CONFIG_QSPI_BOOT 76 static void convert_serdes_mux(int type, int need_reset); 77 78 void cpld_show(void) 79 { 80 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 81 82 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 83 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 84 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 85 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 86 in_8(&cpld_data->vbank) & BANK_MASK); 87 88 #ifdef CONFIG_DEBUG 89 printf("soft_mux_on =%x\n", 90 in_8(&cpld_data->soft_mux_on)); 91 printf("cfg_rcw_src1 =%x\n", 92 in_8(&cpld_data->cfg_rcw_src1)); 93 printf("cfg_rcw_src2 =%x\n", 94 in_8(&cpld_data->cfg_rcw_src2)); 95 printf("vbank =%x\n", 96 in_8(&cpld_data->vbank)); 97 printf("gpio =%x\n", 98 in_8(&cpld_data->gpio)); 99 printf("i2c3_ifc_mux =%x\n", 100 in_8(&cpld_data->i2c3_ifc_mux)); 101 printf("mux_spi2 =%x\n", 102 in_8(&cpld_data->mux_spi2)); 103 printf("can3_usb2_mux =%x\n", 104 in_8(&cpld_data->can3_usb2_mux)); 105 printf("qe_lcd_mux =%x\n", 106 in_8(&cpld_data->qe_lcd_mux)); 107 printf("serdes_mux =%x\n", 108 in_8(&cpld_data->serdes_mux)); 109 #endif 110 } 111 #endif 112 113 int checkboard(void) 114 { 115 puts("Board: LS1021ATWR\n"); 116 #ifndef CONFIG_QSPI_BOOT 117 cpld_show(); 118 #endif 119 120 return 0; 121 } 122 123 void ddrmc_init(void) 124 { 125 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 126 127 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 128 129 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 130 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 131 132 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 133 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 134 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 135 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 136 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 137 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 138 139 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 140 141 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 142 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 143 144 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 145 146 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 147 148 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 149 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 150 151 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 152 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 153 154 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 155 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 156 157 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 158 udelay(1); 159 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN); 160 } 161 162 int dram_init(void) 163 { 164 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 165 ddrmc_init(); 166 #endif 167 168 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 169 return 0; 170 } 171 172 #ifdef CONFIG_FSL_ESDHC 173 struct fsl_esdhc_cfg esdhc_cfg[1] = { 174 {CONFIG_SYS_FSL_ESDHC_ADDR}, 175 }; 176 177 int board_mmc_init(bd_t *bis) 178 { 179 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 180 181 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 182 } 183 #endif 184 185 #ifdef CONFIG_TSEC_ENET 186 int board_eth_init(bd_t *bis) 187 { 188 struct fsl_pq_mdio_info mdio_info; 189 struct tsec_info_struct tsec_info[4]; 190 int num = 0; 191 192 #ifdef CONFIG_TSEC1 193 SET_STD_TSEC_INFO(tsec_info[num], 1); 194 if (is_serdes_configured(SGMII_TSEC1)) { 195 puts("eTSEC1 is in sgmii mode.\n"); 196 tsec_info[num].flags |= TSEC_SGMII; 197 } 198 num++; 199 #endif 200 #ifdef CONFIG_TSEC2 201 SET_STD_TSEC_INFO(tsec_info[num], 2); 202 if (is_serdes_configured(SGMII_TSEC2)) { 203 puts("eTSEC2 is in sgmii mode.\n"); 204 tsec_info[num].flags |= TSEC_SGMII; 205 } 206 num++; 207 #endif 208 #ifdef CONFIG_TSEC3 209 SET_STD_TSEC_INFO(tsec_info[num], 3); 210 num++; 211 #endif 212 if (!num) { 213 printf("No TSECs initialized\n"); 214 return 0; 215 } 216 217 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 218 mdio_info.name = DEFAULT_MII_NAME; 219 fsl_pq_mdio_init(bis, &mdio_info); 220 221 tsec_eth_init(bis, tsec_info, num); 222 223 return pci_eth_init(bis); 224 } 225 #endif 226 227 #ifndef CONFIG_QSPI_BOOT 228 int config_serdes_mux(void) 229 { 230 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 231 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 232 233 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 234 switch (protocol) { 235 case 0x10: 236 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 237 convert_serdes_mux(LANED_PCIEX2 | 238 LANEC_PCIEX1, KEEP_STATUS); 239 break; 240 case 0x20: 241 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 242 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 243 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 244 break; 245 case 0x30: 246 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 247 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 248 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 249 break; 250 case 0x70: 251 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 252 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 253 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 254 break; 255 } 256 257 return 0; 258 } 259 #endif 260 261 int board_early_init_f(void) 262 { 263 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 264 265 #ifdef CONFIG_TSEC_ENET 266 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 267 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 268 #endif 269 270 #ifdef CONFIG_FSL_IFC 271 init_early_memctl_regs(); 272 #endif 273 274 #ifdef CONFIG_FSL_DCU_FB 275 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 276 #endif 277 278 #ifdef CONFIG_FSL_QSPI 279 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 280 #endif 281 282 return 0; 283 } 284 285 #ifdef CONFIG_SPL_BUILD 286 void board_init_f(ulong dummy) 287 { 288 /* Set global data pointer */ 289 gd = &gdata; 290 291 /* Clear the BSS */ 292 memset(__bss_start, 0, __bss_end - __bss_start); 293 294 get_clocks(); 295 296 preloader_console_init(); 297 298 dram_init(); 299 300 board_init_r(NULL, 0); 301 } 302 #endif 303 304 int board_init(void) 305 { 306 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 307 308 /* 309 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register 310 * All transactions are treated as non-shareable 311 */ 312 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 313 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 314 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 315 316 #ifndef CONFIG_SYS_FSL_NO_SERDES 317 fsl_serdes_init(); 318 #ifndef CONFIG_QSPI_BOOT 319 config_serdes_mux(); 320 #endif 321 #endif 322 323 #ifdef CONFIG_U_QE 324 u_qe_init(); 325 #endif 326 327 return 0; 328 } 329 330 #if defined(CONFIG_MISC_INIT_R) 331 int misc_init_r(void) 332 { 333 #ifdef CONFIG_FSL_CAAM 334 return sec_init(); 335 #endif 336 } 337 #endif 338 339 int ft_board_setup(void *blob, bd_t *bd) 340 { 341 ft_cpu_setup(blob, bd); 342 343 #ifdef CONFIG_PCIE_LAYERSCAPE 344 ft_pcie_setup(blob, bd); 345 #endif 346 347 return 0; 348 } 349 350 u8 flash_read8(void *addr) 351 { 352 return __raw_readb(addr + 1); 353 } 354 355 void flash_write16(u16 val, void *addr) 356 { 357 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 358 359 __raw_writew(shftval, addr); 360 } 361 362 u16 flash_read16(void *addr) 363 { 364 u16 val = __raw_readw(addr); 365 366 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 367 } 368 369 #ifndef CONFIG_QSPI_BOOT 370 static void convert_flash_bank(char bank) 371 { 372 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 373 374 printf("Now switch to boot from flash bank %d.\n", bank); 375 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 376 cpld_data->vbank = bank; 377 378 printf("Reset board to enable configuration.\n"); 379 cpld_data->system_rst = CONFIG_RESET; 380 } 381 382 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 383 char * const argv[]) 384 { 385 if (argc != 2) 386 return CMD_RET_USAGE; 387 if (strcmp(argv[1], "0") == 0) 388 convert_flash_bank(BOOT_FROM_UPPER_BANK); 389 else if (strcmp(argv[1], "1") == 0) 390 convert_flash_bank(BOOT_FROM_LOWER_BANK); 391 else 392 return CMD_RET_USAGE; 393 394 return 0; 395 } 396 397 U_BOOT_CMD( 398 boot_bank, 2, 0, flash_bank_cmd, 399 "Flash bank Selection Control", 400 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 401 ); 402 403 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 404 char * const argv[]) 405 { 406 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 407 408 if (argc > 2) 409 return CMD_RET_USAGE; 410 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 411 cpld_data->system_rst = CONFIG_RESET; 412 else if (strcmp(argv[1], "init") == 0) 413 cpld_data->global_rst = INIT_RESET; 414 else 415 return CMD_RET_USAGE; 416 417 return 0; 418 } 419 420 U_BOOT_CMD( 421 cpld_reset, 2, 0, cpld_reset_cmd, 422 "Reset via CPLD", 423 "conf\n" 424 " -reset with current CPLD configuration\n" 425 "init\n" 426 " -reset and initial CPLD configuration with default value" 427 428 ); 429 430 static void convert_serdes_mux(int type, int need_reset) 431 { 432 char current_serdes; 433 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 434 435 current_serdes = cpld_data->serdes_mux; 436 437 switch (type) { 438 case LANEB_SATA: 439 current_serdes &= ~MASK_LANE_B; 440 break; 441 case LANEB_SGMII1: 442 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 443 break; 444 case LANEC_SGMII1: 445 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 446 break; 447 case LANED_SGMII2: 448 current_serdes |= MASK_LANE_D; 449 break; 450 case LANEC_PCIEX1: 451 current_serdes |= MASK_LANE_C; 452 break; 453 case (LANED_PCIEX2 | LANEC_PCIEX1): 454 current_serdes |= MASK_LANE_C; 455 current_serdes &= ~MASK_LANE_D; 456 break; 457 default: 458 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 459 return; 460 } 461 462 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 463 cpld_data->serdes_mux = current_serdes; 464 465 if (need_reset == 1) { 466 printf("Reset board to enable configuration\n"); 467 cpld_data->system_rst = CONFIG_RESET; 468 } 469 } 470 471 void print_serdes_mux(void) 472 { 473 char current_serdes; 474 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 475 476 current_serdes = cpld_data->serdes_mux; 477 478 printf("Serdes Lane B: "); 479 if ((current_serdes & MASK_LANE_B) == 0) 480 printf("SATA,\n"); 481 else 482 printf("SGMII 1,\n"); 483 484 printf("Serdes Lane C: "); 485 if ((current_serdes & MASK_LANE_C) == 0) 486 printf("SGMII 1,\n"); 487 else 488 printf("PCIe,\n"); 489 490 printf("Serdes Lane D: "); 491 if ((current_serdes & MASK_LANE_D) == 0) 492 printf("PCIe,\n"); 493 else 494 printf("SGMII 2,\n"); 495 496 printf("SGMII 1 is on lane "); 497 if ((current_serdes & MASK_SGMII) == 0) 498 printf("C.\n"); 499 else 500 printf("B.\n"); 501 } 502 503 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 504 char * const argv[]) 505 { 506 if (argc != 2) 507 return CMD_RET_USAGE; 508 if (strcmp(argv[1], "sata") == 0) { 509 printf("Set serdes lane B to SATA.\n"); 510 convert_serdes_mux(LANEB_SATA, NEED_RESET); 511 } else if (strcmp(argv[1], "sgmii1b") == 0) { 512 printf("Set serdes lane B to SGMII 1.\n"); 513 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 514 } else if (strcmp(argv[1], "sgmii1c") == 0) { 515 printf("Set serdes lane C to SGMII 1.\n"); 516 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 517 } else if (strcmp(argv[1], "sgmii2") == 0) { 518 printf("Set serdes lane D to SGMII 2.\n"); 519 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 520 } else if (strcmp(argv[1], "pciex1") == 0) { 521 printf("Set serdes lane C to PCIe X1.\n"); 522 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 523 } else if (strcmp(argv[1], "pciex2") == 0) { 524 printf("Set serdes lane C & lane D to PCIe X2.\n"); 525 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 526 } else if (strcmp(argv[1], "show") == 0) { 527 print_serdes_mux(); 528 } else { 529 return CMD_RET_USAGE; 530 } 531 532 return 0; 533 } 534 535 U_BOOT_CMD( 536 lane_bank, 2, 0, serdes_mux_cmd, 537 "Multiplexed function setting for SerDes Lanes", 538 "sata\n" 539 " -change lane B to sata\n" 540 "lane_bank sgmii1b\n" 541 " -change lane B to SGMII1\n" 542 "lane_bank sgmii1c\n" 543 " -change lane C to SGMII1\n" 544 "lane_bank sgmii2\n" 545 " -change lane D to SGMII2\n" 546 "lane_bank pciex1\n" 547 " -change lane C to PCIeX1\n" 548 "lane_bank pciex2\n" 549 " -change lane C & lane D to PCIeX2\n" 550 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 551 ); 552 #endif 553