1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
15 #include <asm/arch/ls102xa_sata.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_csu.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_immap.h>
22 #include <netdev.h>
23 #include <fsl_mdio.h>
24 #include <tsec.h>
25 #include <fsl_sec.h>
26 #include <fsl_devdis.h>
27 #include <spl.h>
28 #include "../common/sleep.h"
29 #ifdef CONFIG_U_QE
30 #include <fsl_qe.h>
31 #endif
32 #include <fsl_validate.h>
33 
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #define VERSION_MASK		0x00FF
38 #define BANK_MASK		0x0001
39 #define CONFIG_RESET		0x1
40 #define INIT_RESET		0x1
41 
42 #define CPLD_SET_MUX_SERDES	0x20
43 #define CPLD_SET_BOOT_BANK	0x40
44 
45 #define BOOT_FROM_UPPER_BANK	0x0
46 #define BOOT_FROM_LOWER_BANK	0x1
47 
48 #define LANEB_SATA		(0x01)
49 #define LANEB_SGMII1		(0x02)
50 #define LANEC_SGMII1		(0x04)
51 #define LANEC_PCIEX1		(0x08)
52 #define LANED_PCIEX2		(0x10)
53 #define LANED_SGMII2		(0x20)
54 
55 #define MASK_LANE_B		0x1
56 #define MASK_LANE_C		0x2
57 #define MASK_LANE_D		0x4
58 #define MASK_SGMII		0x8
59 
60 #define KEEP_STATUS		0x0
61 #define NEED_RESET		0x1
62 
63 #define SOFT_MUX_ON_I2C3_IFC	0x2
64 #define SOFT_MUX_ON_CAN3_USB2	0x8
65 #define SOFT_MUX_ON_QE_LCD	0x10
66 
67 #define PIN_I2C3_IFC_MUX_I2C3	0x0
68 #define PIN_I2C3_IFC_MUX_IFC	0x1
69 #define PIN_CAN3_USB2_MUX_USB2	0x0
70 #define PIN_CAN3_USB2_MUX_CAN3	0x1
71 #define PIN_QE_LCD_MUX_LCD	0x0
72 #define PIN_QE_LCD_MUX_QE	0x1
73 
74 struct cpld_data {
75 	u8 cpld_ver;		/* cpld revision */
76 	u8 cpld_ver_sub;	/* cpld sub revision */
77 	u8 pcba_ver;		/* pcb revision number */
78 	u8 system_rst;		/* reset system by cpld */
79 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
80 	u8 cfg_rcw_src1;	/* Reset config word 1 */
81 	u8 cfg_rcw_src2;	/* Reset config word 2 */
82 	u8 vbank;		/* Flash bank selection Control */
83 	u8 gpio;		/* GPIO for TWR-ELEV */
84 	u8 i2c3_ifc_mux;
85 	u8 mux_spi2;
86 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
87 	u8 qe_lcd_mux;		/* QE and LCD Selection */
88 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
89 	u8 global_rst;		/* reset with init CPLD reg to default */
90 	u8 rev1;		/* Reserved */
91 	u8 rev2;		/* Reserved */
92 };
93 
94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
95 static void convert_serdes_mux(int type, int need_reset);
96 
97 void cpld_show(void)
98 {
99 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
100 
101 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
102 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
103 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
104 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
105 	       in_8(&cpld_data->vbank) & BANK_MASK);
106 
107 #ifdef CONFIG_DEBUG
108 	printf("soft_mux_on =%x\n",
109 	       in_8(&cpld_data->soft_mux_on));
110 	printf("cfg_rcw_src1 =%x\n",
111 	       in_8(&cpld_data->cfg_rcw_src1));
112 	printf("cfg_rcw_src2 =%x\n",
113 	       in_8(&cpld_data->cfg_rcw_src2));
114 	printf("vbank =%x\n",
115 	       in_8(&cpld_data->vbank));
116 	printf("gpio =%x\n",
117 	       in_8(&cpld_data->gpio));
118 	printf("i2c3_ifc_mux =%x\n",
119 	       in_8(&cpld_data->i2c3_ifc_mux));
120 	printf("mux_spi2 =%x\n",
121 	       in_8(&cpld_data->mux_spi2));
122 	printf("can3_usb2_mux =%x\n",
123 	       in_8(&cpld_data->can3_usb2_mux));
124 	printf("qe_lcd_mux =%x\n",
125 	       in_8(&cpld_data->qe_lcd_mux));
126 	printf("serdes_mux =%x\n",
127 	       in_8(&cpld_data->serdes_mux));
128 #endif
129 }
130 #endif
131 
132 int checkboard(void)
133 {
134 	puts("Board: LS1021ATWR\n");
135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
136 	cpld_show();
137 #endif
138 
139 	return 0;
140 }
141 
142 void ddrmc_init(void)
143 {
144 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
145 	u32 temp_sdram_cfg, tmp;
146 
147 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
148 
149 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
150 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
151 
152 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
153 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
154 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
155 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
156 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
157 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
158 
159 #ifdef CONFIG_DEEP_SLEEP
160 	if (is_warm_boot()) {
161 		out_be32(&ddr->sdram_cfg_2,
162 			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
163 		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
164 		out_be32(&ddr->init_ext_addr, (1 << 31));
165 
166 		/* DRAM VRef will not be trained */
167 		out_be32(&ddr->ddr_cdr2,
168 			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
169 	} else
170 #endif
171 	{
172 		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
173 		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
174 	}
175 
176 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
177 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
178 
179 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
180 
181 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
182 
183 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
184 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
185 
186 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
187 
188 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
189 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
190 
191 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
192 
193 	/* DDR erratum A-009942 */
194 	tmp = in_be32(&ddr->debug[28]);
195 	out_be32(&ddr->debug[28], tmp | 0x0070006f);
196 
197 	udelay(1);
198 
199 #ifdef CONFIG_DEEP_SLEEP
200 	if (is_warm_boot()) {
201 		/* enter self-refresh */
202 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
203 		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
204 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
205 
206 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
207 	} else
208 #endif
209 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
210 
211 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
212 
213 #ifdef CONFIG_DEEP_SLEEP
214 	if (is_warm_boot()) {
215 		/* exit self-refresh */
216 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
217 		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
218 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
219 	}
220 #endif
221 }
222 
223 int dram_init(void)
224 {
225 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
226 	ddrmc_init();
227 #endif
228 
229 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
230 
231 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
232 	fsl_dp_resume();
233 #endif
234 
235 	return 0;
236 }
237 
238 #ifdef CONFIG_FSL_ESDHC
239 struct fsl_esdhc_cfg esdhc_cfg[1] = {
240 	{CONFIG_SYS_FSL_ESDHC_ADDR},
241 };
242 
243 int board_mmc_init(bd_t *bis)
244 {
245 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
246 
247 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
248 }
249 #endif
250 
251 int board_eth_init(bd_t *bis)
252 {
253 #ifdef CONFIG_TSEC_ENET
254 	struct fsl_pq_mdio_info mdio_info;
255 	struct tsec_info_struct tsec_info[4];
256 	int num = 0;
257 
258 #ifdef CONFIG_TSEC1
259 	SET_STD_TSEC_INFO(tsec_info[num], 1);
260 	if (is_serdes_configured(SGMII_TSEC1)) {
261 		puts("eTSEC1 is in sgmii mode.\n");
262 		tsec_info[num].flags |= TSEC_SGMII;
263 	}
264 	num++;
265 #endif
266 #ifdef CONFIG_TSEC2
267 	SET_STD_TSEC_INFO(tsec_info[num], 2);
268 	if (is_serdes_configured(SGMII_TSEC2)) {
269 		puts("eTSEC2 is in sgmii mode.\n");
270 		tsec_info[num].flags |= TSEC_SGMII;
271 	}
272 	num++;
273 #endif
274 #ifdef CONFIG_TSEC3
275 	SET_STD_TSEC_INFO(tsec_info[num], 3);
276 	num++;
277 #endif
278 	if (!num) {
279 		printf("No TSECs initialized\n");
280 		return 0;
281 	}
282 
283 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
284 	mdio_info.name = DEFAULT_MII_NAME;
285 	fsl_pq_mdio_init(bis, &mdio_info);
286 
287 	tsec_eth_init(bis, tsec_info, num);
288 #endif
289 
290 	return pci_eth_init(bis);
291 }
292 
293 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
294 int config_serdes_mux(void)
295 {
296 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
297 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
298 
299 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
300 	switch (protocol) {
301 	case 0x10:
302 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
303 		convert_serdes_mux(LANED_PCIEX2 |
304 				LANEC_PCIEX1, KEEP_STATUS);
305 		break;
306 	case 0x20:
307 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
308 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
309 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
310 		break;
311 	case 0x30:
312 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
313 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
314 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
315 		break;
316 	case 0x70:
317 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
318 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
319 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
320 		break;
321 	}
322 
323 	return 0;
324 }
325 #endif
326 
327 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
328 int config_board_mux(void)
329 {
330 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
331 	int conflict_flag;
332 
333 	conflict_flag = 0;
334 	if (hwconfig("i2c3")) {
335 		conflict_flag++;
336 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
337 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
338 	}
339 
340 	if (hwconfig("ifc")) {
341 		conflict_flag++;
342 		/* some signals can not enable simultaneous*/
343 		if (conflict_flag > 1)
344 			goto conflict;
345 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
346 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
347 	}
348 
349 	conflict_flag = 0;
350 	if (hwconfig("usb2")) {
351 		conflict_flag++;
352 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
353 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
354 	}
355 
356 	if (hwconfig("can3")) {
357 		conflict_flag++;
358 		/* some signals can not enable simultaneous*/
359 		if (conflict_flag > 1)
360 			goto conflict;
361 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
362 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
363 	}
364 
365 	conflict_flag = 0;
366 	if (hwconfig("lcd")) {
367 		conflict_flag++;
368 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
369 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
370 	}
371 
372 	if (hwconfig("qe")) {
373 		conflict_flag++;
374 		/* some signals can not enable simultaneous*/
375 		if (conflict_flag > 1)
376 			goto conflict;
377 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
378 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
379 	}
380 
381 	return 0;
382 
383 conflict:
384 	printf("WARNING: pin conflict! MUX setting may failed!\n");
385 	return 0;
386 }
387 #endif
388 
389 int board_early_init_f(void)
390 {
391 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
392 
393 #ifdef CONFIG_TSEC_ENET
394 	/* clear BD & FR bits for BE BD's and frame data */
395 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
396 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
397 #endif
398 
399 #ifdef CONFIG_FSL_IFC
400 	init_early_memctl_regs();
401 #endif
402 
403 	arch_soc_init();
404 
405 #if defined(CONFIG_DEEP_SLEEP)
406 	if (is_warm_boot()) {
407 		timer_init();
408 		dram_init();
409 	}
410 #endif
411 
412 	return 0;
413 }
414 
415 #ifdef CONFIG_SPL_BUILD
416 void board_init_f(ulong dummy)
417 {
418 	void (*second_uboot)(void);
419 
420 	/* Clear the BSS */
421 	memset(__bss_start, 0, __bss_end - __bss_start);
422 
423 	get_clocks();
424 
425 #if defined(CONFIG_DEEP_SLEEP)
426 	if (is_warm_boot())
427 		fsl_dp_disable_console();
428 #endif
429 
430 	preloader_console_init();
431 
432 	dram_init();
433 
434 	/* Allow OCRAM access permission as R/W */
435 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
436 	enable_layerscape_ns_access();
437 	enable_layerscape_ns_access();
438 #endif
439 
440 	/*
441 	 * if it is woken up from deep sleep, then jump to second
442 	 * stage uboot and continue executing without recopying
443 	 * it from SD since it has already been reserved in memeory
444 	 * in last boot.
445 	 */
446 	if (is_warm_boot()) {
447 		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
448 		second_uboot();
449 	}
450 
451 	board_init_r(NULL, 0);
452 }
453 #endif
454 
455 #ifdef CONFIG_DEEP_SLEEP
456 /* program the regulator (MC34VR500) to support deep sleep */
457 void ls1twr_program_regulator(void)
458 {
459 	unsigned int i2c_bus;
460 	u8 i2c_device_id;
461 
462 #define LS1TWR_I2C_BUS_MC34VR500	1
463 #define MC34VR500_ADDR			0x8
464 #define MC34VR500_DEVICEID		0x4
465 #define MC34VR500_DEVICEID_MASK		0x0f
466 
467 	i2c_bus = i2c_get_bus_num();
468 	i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
469 	i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
470 					MC34VR500_DEVICEID_MASK;
471 	if (i2c_device_id != MC34VR500_DEVICEID) {
472 		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
473 		return;
474 	}
475 
476 	i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
477 	i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
478 	i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
479 	i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
480 	i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
481 
482 	i2c_set_bus_num(i2c_bus);
483 }
484 #endif
485 
486 int board_init(void)
487 {
488 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
489 	erratum_a010315();
490 #endif
491 
492 #ifndef CONFIG_SYS_FSL_NO_SERDES
493 	fsl_serdes_init();
494 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
495 	config_serdes_mux();
496 #endif
497 #endif
498 
499 	ls102xa_smmu_stream_id_init();
500 
501 #ifdef CONFIG_U_QE
502 	u_qe_init();
503 #endif
504 
505 #ifdef CONFIG_DEEP_SLEEP
506 	ls1twr_program_regulator();
507 #endif
508 	return 0;
509 }
510 
511 #if defined(CONFIG_SPL_BUILD)
512 void spl_board_init(void)
513 {
514 	ls102xa_smmu_stream_id_init();
515 }
516 #endif
517 
518 #ifdef CONFIG_BOARD_LATE_INIT
519 int board_late_init(void)
520 {
521 #ifdef CONFIG_SCSI_AHCI_PLAT
522 	ls1021a_sata_init();
523 #endif
524 #ifdef CONFIG_CHAIN_OF_TRUST
525 	fsl_setenv_chain_of_trust();
526 #endif
527 
528 	return 0;
529 }
530 #endif
531 
532 #if defined(CONFIG_MISC_INIT_R)
533 int misc_init_r(void)
534 {
535 #ifdef CONFIG_FSL_DEVICE_DISABLE
536 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
537 #endif
538 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
539 	config_board_mux();
540 #endif
541 
542 #ifdef CONFIG_FSL_CAAM
543 	return sec_init();
544 #endif
545 }
546 #endif
547 
548 #if defined(CONFIG_DEEP_SLEEP)
549 void board_sleep_prepare(void)
550 {
551 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
552 	enable_layerscape_ns_access();
553 #endif
554 }
555 #endif
556 
557 int ft_board_setup(void *blob, bd_t *bd)
558 {
559 	ft_cpu_setup(blob, bd);
560 
561 #ifdef CONFIG_PCI
562 	ft_pci_setup(blob, bd);
563 #endif
564 
565 	return 0;
566 }
567 
568 u8 flash_read8(void *addr)
569 {
570 	return __raw_readb(addr + 1);
571 }
572 
573 void flash_write16(u16 val, void *addr)
574 {
575 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
576 
577 	__raw_writew(shftval, addr);
578 }
579 
580 u16 flash_read16(void *addr)
581 {
582 	u16 val = __raw_readw(addr);
583 
584 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
585 }
586 
587 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
588 static void convert_flash_bank(char bank)
589 {
590 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
591 
592 	printf("Now switch to boot from flash bank %d.\n", bank);
593 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
594 	cpld_data->vbank = bank;
595 
596 	printf("Reset board to enable configuration.\n");
597 	cpld_data->system_rst = CONFIG_RESET;
598 }
599 
600 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
601 			  char * const argv[])
602 {
603 	if (argc != 2)
604 		return CMD_RET_USAGE;
605 	if (strcmp(argv[1], "0") == 0)
606 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
607 	else if (strcmp(argv[1], "1") == 0)
608 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
609 	else
610 		return CMD_RET_USAGE;
611 
612 	return 0;
613 }
614 
615 U_BOOT_CMD(
616 	boot_bank, 2, 0, flash_bank_cmd,
617 	"Flash bank Selection Control",
618 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
619 );
620 
621 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
622 			  char * const argv[])
623 {
624 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
625 
626 	if (argc > 2)
627 		return CMD_RET_USAGE;
628 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
629 		cpld_data->system_rst = CONFIG_RESET;
630 	else if (strcmp(argv[1], "init") == 0)
631 		cpld_data->global_rst = INIT_RESET;
632 	else
633 		return CMD_RET_USAGE;
634 
635 	return 0;
636 }
637 
638 U_BOOT_CMD(
639 	cpld_reset, 2, 0, cpld_reset_cmd,
640 	"Reset via CPLD",
641 	"conf\n"
642 	"	-reset with current CPLD configuration\n"
643 	"init\n"
644 	"	-reset and initial CPLD configuration with default value"
645 
646 );
647 
648 static void convert_serdes_mux(int type, int need_reset)
649 {
650 	char current_serdes;
651 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
652 
653 	current_serdes = cpld_data->serdes_mux;
654 
655 	switch (type) {
656 	case LANEB_SATA:
657 		current_serdes &= ~MASK_LANE_B;
658 		break;
659 	case LANEB_SGMII1:
660 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
661 		break;
662 	case LANEC_SGMII1:
663 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
664 		break;
665 	case LANED_SGMII2:
666 		current_serdes |= MASK_LANE_D;
667 		break;
668 	case LANEC_PCIEX1:
669 		current_serdes |= MASK_LANE_C;
670 		break;
671 	case (LANED_PCIEX2 | LANEC_PCIEX1):
672 		current_serdes |= MASK_LANE_C;
673 		current_serdes &= ~MASK_LANE_D;
674 		break;
675 	default:
676 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
677 		return;
678 	}
679 
680 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
681 	cpld_data->serdes_mux = current_serdes;
682 
683 	if (need_reset == 1) {
684 		printf("Reset board to enable configuration\n");
685 		cpld_data->system_rst = CONFIG_RESET;
686 	}
687 }
688 
689 void print_serdes_mux(void)
690 {
691 	char current_serdes;
692 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
693 
694 	current_serdes = cpld_data->serdes_mux;
695 
696 	printf("Serdes Lane B: ");
697 	if ((current_serdes & MASK_LANE_B) == 0)
698 		printf("SATA,\n");
699 	else
700 		printf("SGMII 1,\n");
701 
702 	printf("Serdes Lane C: ");
703 	if ((current_serdes & MASK_LANE_C) == 0)
704 		printf("SGMII 1,\n");
705 	else
706 		printf("PCIe,\n");
707 
708 	printf("Serdes Lane D: ");
709 	if ((current_serdes & MASK_LANE_D) == 0)
710 		printf("PCIe,\n");
711 	else
712 		printf("SGMII 2,\n");
713 
714 	printf("SGMII 1 is on lane ");
715 	if ((current_serdes & MASK_SGMII) == 0)
716 		printf("C.\n");
717 	else
718 		printf("B.\n");
719 }
720 
721 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
722 			  char * const argv[])
723 {
724 	if (argc != 2)
725 		return CMD_RET_USAGE;
726 	if (strcmp(argv[1], "sata") == 0) {
727 		printf("Set serdes lane B to SATA.\n");
728 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
729 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
730 		printf("Set serdes lane B to SGMII 1.\n");
731 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
732 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
733 		printf("Set serdes lane C to SGMII 1.\n");
734 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
735 	} else if (strcmp(argv[1], "sgmii2") == 0) {
736 		printf("Set serdes lane D to SGMII 2.\n");
737 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
738 	} else if (strcmp(argv[1], "pciex1") == 0) {
739 		printf("Set serdes lane C to PCIe X1.\n");
740 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
741 	} else if (strcmp(argv[1], "pciex2") == 0) {
742 		printf("Set serdes lane C & lane D to PCIe X2.\n");
743 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
744 	} else if (strcmp(argv[1], "show") == 0) {
745 		print_serdes_mux();
746 	} else {
747 		return CMD_RET_USAGE;
748 	}
749 
750 	return 0;
751 }
752 
753 U_BOOT_CMD(
754 	lane_bank, 2, 0, serdes_mux_cmd,
755 	"Multiplexed function setting for SerDes Lanes",
756 	"sata\n"
757 	"	-change lane B to sata\n"
758 	"lane_bank sgmii1b\n"
759 	"	-change lane B to SGMII1\n"
760 	"lane_bank sgmii1c\n"
761 	"	-change lane C to SGMII1\n"
762 	"lane_bank sgmii2\n"
763 	"	-change lane D to SGMII2\n"
764 	"lane_bank pciex1\n"
765 	"	-change lane C to PCIeX1\n"
766 	"lane_bank pciex2\n"
767 	"	-change lane C & lane D to PCIeX2\n"
768 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
769 );
770 #endif
771