1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ns_access.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
15 #include <asm/pcie_layerscape.h>
16 #include <mmc.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_ifc.h>
19 #include <netdev.h>
20 #include <fsl_mdio.h>
21 #include <tsec.h>
22 #include <fsl_sec.h>
23 #include <spl.h>
24 #ifdef CONFIG_U_QE
25 #include "../../../drivers/qe/qe.h"
26 #endif
27 
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 #define VERSION_MASK		0x00FF
32 #define BANK_MASK		0x0001
33 #define CONFIG_RESET		0x1
34 #define INIT_RESET		0x1
35 
36 #define CPLD_SET_MUX_SERDES	0x20
37 #define CPLD_SET_BOOT_BANK	0x40
38 
39 #define BOOT_FROM_UPPER_BANK	0x0
40 #define BOOT_FROM_LOWER_BANK	0x1
41 
42 #define LANEB_SATA		(0x01)
43 #define LANEB_SGMII1		(0x02)
44 #define LANEC_SGMII1		(0x04)
45 #define LANEC_PCIEX1		(0x08)
46 #define LANED_PCIEX2		(0x10)
47 #define LANED_SGMII2		(0x20)
48 
49 #define MASK_LANE_B		0x1
50 #define MASK_LANE_C		0x2
51 #define MASK_LANE_D		0x4
52 #define MASK_SGMII		0x8
53 
54 #define KEEP_STATUS		0x0
55 #define NEED_RESET		0x1
56 
57 struct cpld_data {
58 	u8 cpld_ver;		/* cpld revision */
59 	u8 cpld_ver_sub;	/* cpld sub revision */
60 	u8 pcba_ver;		/* pcb revision number */
61 	u8 system_rst;		/* reset system by cpld */
62 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
63 	u8 cfg_rcw_src1;	/* Reset config word 1 */
64 	u8 cfg_rcw_src2;	/* Reset config word 2 */
65 	u8 vbank;		/* Flash bank selection Control */
66 	u8 gpio;		/* GPIO for TWR-ELEV */
67 	u8 i2c3_ifc_mux;
68 	u8 mux_spi2;
69 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
70 	u8 qe_lcd_mux;		/* QE and LCD Selection */
71 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
72 	u8 global_rst;		/* reset with init CPLD reg to default */
73 	u8 rev1;		/* Reserved */
74 	u8 rev2;		/* Reserved */
75 };
76 
77 #ifndef CONFIG_QSPI_BOOT
78 static void convert_serdes_mux(int type, int need_reset);
79 
80 void cpld_show(void)
81 {
82 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
83 
84 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
85 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
86 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
87 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
88 	       in_8(&cpld_data->vbank) & BANK_MASK);
89 
90 #ifdef CONFIG_DEBUG
91 	printf("soft_mux_on =%x\n",
92 	       in_8(&cpld_data->soft_mux_on));
93 	printf("cfg_rcw_src1 =%x\n",
94 	       in_8(&cpld_data->cfg_rcw_src1));
95 	printf("cfg_rcw_src2 =%x\n",
96 	       in_8(&cpld_data->cfg_rcw_src2));
97 	printf("vbank =%x\n",
98 	       in_8(&cpld_data->vbank));
99 	printf("gpio =%x\n",
100 	       in_8(&cpld_data->gpio));
101 	printf("i2c3_ifc_mux =%x\n",
102 	       in_8(&cpld_data->i2c3_ifc_mux));
103 	printf("mux_spi2 =%x\n",
104 	       in_8(&cpld_data->mux_spi2));
105 	printf("can3_usb2_mux =%x\n",
106 	       in_8(&cpld_data->can3_usb2_mux));
107 	printf("qe_lcd_mux =%x\n",
108 	       in_8(&cpld_data->qe_lcd_mux));
109 	printf("serdes_mux =%x\n",
110 	       in_8(&cpld_data->serdes_mux));
111 #endif
112 }
113 #endif
114 
115 int checkboard(void)
116 {
117 	puts("Board: LS1021ATWR\n");
118 #ifndef CONFIG_QSPI_BOOT
119 	cpld_show();
120 #endif
121 
122 	return 0;
123 }
124 
125 void ddrmc_init(void)
126 {
127 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
128 
129 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
130 
131 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
132 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
133 
134 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
135 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
136 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
137 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
138 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
139 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
140 
141 	out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
142 
143 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
144 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
145 
146 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
147 
148 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
149 
150 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
151 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
152 
153 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
154 	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
155 
156 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
157 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
158 
159 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
160 	udelay(1);
161 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
162 }
163 
164 int dram_init(void)
165 {
166 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
167 	ddrmc_init();
168 #endif
169 
170 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
171 	return 0;
172 }
173 
174 #ifdef CONFIG_FSL_ESDHC
175 struct fsl_esdhc_cfg esdhc_cfg[1] = {
176 	{CONFIG_SYS_FSL_ESDHC_ADDR},
177 };
178 
179 int board_mmc_init(bd_t *bis)
180 {
181 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
182 
183 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
184 }
185 #endif
186 
187 #ifdef CONFIG_TSEC_ENET
188 int board_eth_init(bd_t *bis)
189 {
190 	struct fsl_pq_mdio_info mdio_info;
191 	struct tsec_info_struct tsec_info[4];
192 	int num = 0;
193 
194 #ifdef CONFIG_TSEC1
195 	SET_STD_TSEC_INFO(tsec_info[num], 1);
196 	if (is_serdes_configured(SGMII_TSEC1)) {
197 		puts("eTSEC1 is in sgmii mode.\n");
198 		tsec_info[num].flags |= TSEC_SGMII;
199 	}
200 	num++;
201 #endif
202 #ifdef CONFIG_TSEC2
203 	SET_STD_TSEC_INFO(tsec_info[num], 2);
204 	if (is_serdes_configured(SGMII_TSEC2)) {
205 		puts("eTSEC2 is in sgmii mode.\n");
206 		tsec_info[num].flags |= TSEC_SGMII;
207 	}
208 	num++;
209 #endif
210 #ifdef CONFIG_TSEC3
211 	SET_STD_TSEC_INFO(tsec_info[num], 3);
212 	num++;
213 #endif
214 	if (!num) {
215 		printf("No TSECs initialized\n");
216 		return 0;
217 	}
218 
219 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
220 	mdio_info.name = DEFAULT_MII_NAME;
221 	fsl_pq_mdio_init(bis, &mdio_info);
222 
223 	tsec_eth_init(bis, tsec_info, num);
224 
225 	return pci_eth_init(bis);
226 }
227 #endif
228 
229 #ifndef CONFIG_QSPI_BOOT
230 int config_serdes_mux(void)
231 {
232 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
233 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
234 
235 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
236 	switch (protocol) {
237 	case 0x10:
238 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
239 		convert_serdes_mux(LANED_PCIEX2 |
240 				LANEC_PCIEX1, KEEP_STATUS);
241 		break;
242 	case 0x20:
243 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
244 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
245 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
246 		break;
247 	case 0x30:
248 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
249 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
250 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
251 		break;
252 	case 0x70:
253 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
254 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
255 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
256 		break;
257 	}
258 
259 	return 0;
260 }
261 #endif
262 
263 int board_early_init_f(void)
264 {
265 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
266 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
267 
268 #ifdef CONFIG_TSEC_ENET
269 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
270 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
271 #endif
272 
273 #ifdef CONFIG_FSL_IFC
274 	init_early_memctl_regs();
275 #endif
276 
277 #ifdef CONFIG_FSL_DCU_FB
278 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
279 #endif
280 
281 #ifdef CONFIG_FSL_QSPI
282 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
283 #endif
284 
285 	/*
286 	 * Enable snoop requests and DVM message requests for
287 	 * Slave insterface S4 (A7 core cluster)
288 	 */
289 	out_le32(&cci->slave[4].snoop_ctrl,
290 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
291 
292 	/*
293 	 * Set CCI-400 Slave interface S1, S2 Shareable Override Register
294 	 * All transactions are treated as non-shareable
295 	 */
296 	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
297 	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
298 
299 	return 0;
300 }
301 
302 #ifdef CONFIG_SPL_BUILD
303 void board_init_f(ulong dummy)
304 {
305 	/* Clear the BSS */
306 	memset(__bss_start, 0, __bss_end - __bss_start);
307 
308 	get_clocks();
309 
310 	preloader_console_init();
311 
312 	dram_init();
313 
314 	board_init_r(NULL, 0);
315 }
316 #endif
317 
318 #ifdef CONFIG_LS102XA_NS_ACCESS
319 static struct csu_ns_dev ns_dev[] = {
320 	{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
321 	{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
322 	{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
323 	{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
324 	{ CSU_CSLX_OCRAM, CSU_ALL_RW },
325 	{ CSU_CSLX_GIC, CSU_ALL_RW },
326 	{ CSU_CSLX_PCIE1, CSU_ALL_RW },
327 	{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
328 	{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
329 	{ CSU_CSLX_PCIE2, CSU_ALL_RW },
330 	{ CSU_CSLX_SATA, CSU_ALL_RW },
331 	{ CSU_CSLX_USB3, CSU_ALL_RW },
332 	{ CSU_CSLX_SERDES, CSU_ALL_RW },
333 	{ CSU_CSLX_QDMA, CSU_ALL_RW },
334 	{ CSU_CSLX_LPUART2, CSU_ALL_RW },
335 	{ CSU_CSLX_LPUART1, CSU_ALL_RW },
336 	{ CSU_CSLX_LPUART4, CSU_ALL_RW },
337 	{ CSU_CSLX_LPUART3, CSU_ALL_RW },
338 	{ CSU_CSLX_LPUART6, CSU_ALL_RW },
339 	{ CSU_CSLX_LPUART5, CSU_ALL_RW },
340 	{ CSU_CSLX_DSPI2, CSU_ALL_RW },
341 	{ CSU_CSLX_DSPI1, CSU_ALL_RW },
342 	{ CSU_CSLX_QSPI, CSU_ALL_RW },
343 	{ CSU_CSLX_ESDHC, CSU_ALL_RW },
344 	{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
345 	{ CSU_CSLX_IFC, CSU_ALL_RW },
346 	{ CSU_CSLX_I2C1, CSU_ALL_RW },
347 	{ CSU_CSLX_USB2, CSU_ALL_RW },
348 	{ CSU_CSLX_I2C3, CSU_ALL_RW },
349 	{ CSU_CSLX_I2C2, CSU_ALL_RW },
350 	{ CSU_CSLX_DUART2, CSU_ALL_RW },
351 	{ CSU_CSLX_DUART1, CSU_ALL_RW },
352 	{ CSU_CSLX_WDT2, CSU_ALL_RW },
353 	{ CSU_CSLX_WDT1, CSU_ALL_RW },
354 	{ CSU_CSLX_EDMA, CSU_ALL_RW },
355 	{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
356 	{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
357 	{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
358 	{ CSU_CSLX_DDR, CSU_ALL_RW },
359 	{ CSU_CSLX_QUICC, CSU_ALL_RW },
360 	{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
361 	{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
362 	{ CSU_CSLX_SFP, CSU_ALL_RW },
363 	{ CSU_CSLX_TMU, CSU_ALL_RW },
364 	{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
365 	{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
366 	{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
367 	{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
368 	{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
369 	{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
370 	{ CSU_CSLX_GPIO2, CSU_ALL_RW },
371 	{ CSU_CSLX_GPIO1, CSU_ALL_RW },
372 	{ CSU_CSLX_GPIO4, CSU_ALL_RW },
373 	{ CSU_CSLX_GPIO3, CSU_ALL_RW },
374 	{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
375 	{ CSU_CSLX_CSU, CSU_ALL_RW },
376 	{ CSU_CSLX_ASRC, CSU_ALL_RW },
377 	{ CSU_CSLX_SPDIF, CSU_ALL_RW },
378 	{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
379 	{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
380 	{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
381 	{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
382 	{ CSU_CSLX_SAI2, CSU_ALL_RW },
383 	{ CSU_CSLX_SAI1, CSU_ALL_RW },
384 	{ CSU_CSLX_SAI4, CSU_ALL_RW },
385 	{ CSU_CSLX_SAI3, CSU_ALL_RW },
386 	{ CSU_CSLX_FTM2, CSU_ALL_RW },
387 	{ CSU_CSLX_FTM1, CSU_ALL_RW },
388 	{ CSU_CSLX_FTM4, CSU_ALL_RW },
389 	{ CSU_CSLX_FTM3, CSU_ALL_RW },
390 	{ CSU_CSLX_FTM6, CSU_ALL_RW },
391 	{ CSU_CSLX_FTM5, CSU_ALL_RW },
392 	{ CSU_CSLX_FTM8, CSU_ALL_RW },
393 	{ CSU_CSLX_FTM7, CSU_ALL_RW },
394 	{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
395 	{ CSU_CSLX_EPU, CSU_ALL_RW },
396 	{ CSU_CSLX_GDI, CSU_ALL_RW },
397 	{ CSU_CSLX_DDI, CSU_ALL_RW },
398 	{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
399 	{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
400 	{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
401 };
402 #endif
403 
404 struct smmu_stream_id dev_stream_id[] = {
405 	{ 0x100, 0x01, "ETSEC MAC1" },
406 	{ 0x104, 0x02, "ETSEC MAC2" },
407 	{ 0x108, 0x03, "ETSEC MAC3" },
408 	{ 0x10c, 0x04, "PEX1" },
409 	{ 0x110, 0x05, "PEX2" },
410 	{ 0x114, 0x06, "qDMA" },
411 	{ 0x118, 0x07, "SATA" },
412 	{ 0x11c, 0x08, "USB3" },
413 	{ 0x120, 0x09, "QE" },
414 	{ 0x124, 0x0a, "eSDHC" },
415 	{ 0x128, 0x0b, "eMA" },
416 	{ 0x14c, 0x0c, "2D-ACE" },
417 	{ 0x150, 0x0d, "USB2" },
418 	{ 0x18c, 0x0e, "DEBUG" },
419 };
420 
421 int board_init(void)
422 {
423 #ifndef CONFIG_SYS_FSL_NO_SERDES
424 	fsl_serdes_init();
425 #ifndef CONFIG_QSPI_BOOT
426 	config_serdes_mux();
427 #endif
428 #endif
429 
430 	ls102xa_config_smmu_stream_id(dev_stream_id,
431 				      ARRAY_SIZE(dev_stream_id));
432 
433 #ifdef CONFIG_LS102XA_NS_ACCESS
434 	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
435 #endif
436 
437 #ifdef CONFIG_U_QE
438 	u_qe_init();
439 #endif
440 
441 	return 0;
442 }
443 
444 #if defined(CONFIG_MISC_INIT_R)
445 int misc_init_r(void)
446 {
447 #ifdef CONFIG_FSL_CAAM
448 	return sec_init();
449 #endif
450 }
451 #endif
452 
453 int ft_board_setup(void *blob, bd_t *bd)
454 {
455 	ft_cpu_setup(blob, bd);
456 
457 #ifdef CONFIG_PCIE_LAYERSCAPE
458 	ft_pcie_setup(blob, bd);
459 #endif
460 
461 	return 0;
462 }
463 
464 u8 flash_read8(void *addr)
465 {
466 	return __raw_readb(addr + 1);
467 }
468 
469 void flash_write16(u16 val, void *addr)
470 {
471 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
472 
473 	__raw_writew(shftval, addr);
474 }
475 
476 u16 flash_read16(void *addr)
477 {
478 	u16 val = __raw_readw(addr);
479 
480 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
481 }
482 
483 #ifndef CONFIG_QSPI_BOOT
484 static void convert_flash_bank(char bank)
485 {
486 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
487 
488 	printf("Now switch to boot from flash bank %d.\n", bank);
489 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
490 	cpld_data->vbank = bank;
491 
492 	printf("Reset board to enable configuration.\n");
493 	cpld_data->system_rst = CONFIG_RESET;
494 }
495 
496 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
497 			  char * const argv[])
498 {
499 	if (argc != 2)
500 		return CMD_RET_USAGE;
501 	if (strcmp(argv[1], "0") == 0)
502 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
503 	else if (strcmp(argv[1], "1") == 0)
504 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
505 	else
506 		return CMD_RET_USAGE;
507 
508 	return 0;
509 }
510 
511 U_BOOT_CMD(
512 	boot_bank, 2, 0, flash_bank_cmd,
513 	"Flash bank Selection Control",
514 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
515 );
516 
517 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
518 			  char * const argv[])
519 {
520 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
521 
522 	if (argc > 2)
523 		return CMD_RET_USAGE;
524 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
525 		cpld_data->system_rst = CONFIG_RESET;
526 	else if (strcmp(argv[1], "init") == 0)
527 		cpld_data->global_rst = INIT_RESET;
528 	else
529 		return CMD_RET_USAGE;
530 
531 	return 0;
532 }
533 
534 U_BOOT_CMD(
535 	cpld_reset, 2, 0, cpld_reset_cmd,
536 	"Reset via CPLD",
537 	"conf\n"
538 	"	-reset with current CPLD configuration\n"
539 	"init\n"
540 	"	-reset and initial CPLD configuration with default value"
541 
542 );
543 
544 static void convert_serdes_mux(int type, int need_reset)
545 {
546 	char current_serdes;
547 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
548 
549 	current_serdes = cpld_data->serdes_mux;
550 
551 	switch (type) {
552 	case LANEB_SATA:
553 		current_serdes &= ~MASK_LANE_B;
554 		break;
555 	case LANEB_SGMII1:
556 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
557 		break;
558 	case LANEC_SGMII1:
559 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
560 		break;
561 	case LANED_SGMII2:
562 		current_serdes |= MASK_LANE_D;
563 		break;
564 	case LANEC_PCIEX1:
565 		current_serdes |= MASK_LANE_C;
566 		break;
567 	case (LANED_PCIEX2 | LANEC_PCIEX1):
568 		current_serdes |= MASK_LANE_C;
569 		current_serdes &= ~MASK_LANE_D;
570 		break;
571 	default:
572 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
573 		return;
574 	}
575 
576 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
577 	cpld_data->serdes_mux = current_serdes;
578 
579 	if (need_reset == 1) {
580 		printf("Reset board to enable configuration\n");
581 		cpld_data->system_rst = CONFIG_RESET;
582 	}
583 }
584 
585 void print_serdes_mux(void)
586 {
587 	char current_serdes;
588 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
589 
590 	current_serdes = cpld_data->serdes_mux;
591 
592 	printf("Serdes Lane B: ");
593 	if ((current_serdes & MASK_LANE_B) == 0)
594 		printf("SATA,\n");
595 	else
596 		printf("SGMII 1,\n");
597 
598 	printf("Serdes Lane C: ");
599 	if ((current_serdes & MASK_LANE_C) == 0)
600 		printf("SGMII 1,\n");
601 	else
602 		printf("PCIe,\n");
603 
604 	printf("Serdes Lane D: ");
605 	if ((current_serdes & MASK_LANE_D) == 0)
606 		printf("PCIe,\n");
607 	else
608 		printf("SGMII 2,\n");
609 
610 	printf("SGMII 1 is on lane ");
611 	if ((current_serdes & MASK_SGMII) == 0)
612 		printf("C.\n");
613 	else
614 		printf("B.\n");
615 }
616 
617 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
618 			  char * const argv[])
619 {
620 	if (argc != 2)
621 		return CMD_RET_USAGE;
622 	if (strcmp(argv[1], "sata") == 0) {
623 		printf("Set serdes lane B to SATA.\n");
624 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
625 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
626 		printf("Set serdes lane B to SGMII 1.\n");
627 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
628 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
629 		printf("Set serdes lane C to SGMII 1.\n");
630 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
631 	} else if (strcmp(argv[1], "sgmii2") == 0) {
632 		printf("Set serdes lane D to SGMII 2.\n");
633 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
634 	} else if (strcmp(argv[1], "pciex1") == 0) {
635 		printf("Set serdes lane C to PCIe X1.\n");
636 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
637 	} else if (strcmp(argv[1], "pciex2") == 0) {
638 		printf("Set serdes lane C & lane D to PCIe X2.\n");
639 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
640 	} else if (strcmp(argv[1], "show") == 0) {
641 		print_serdes_mux();
642 	} else {
643 		return CMD_RET_USAGE;
644 	}
645 
646 	return 0;
647 }
648 
649 U_BOOT_CMD(
650 	lane_bank, 2, 0, serdes_mux_cmd,
651 	"Multiplexed function setting for SerDes Lanes",
652 	"sata\n"
653 	"	-change lane B to sata\n"
654 	"lane_bank sgmii1b\n"
655 	"	-change lane B to SGMII1\n"
656 	"lane_bank sgmii1c\n"
657 	"	-change lane C to SGMII1\n"
658 	"lane_bank sgmii2\n"
659 	"	-change lane D to SGMII2\n"
660 	"lane_bank pciex1\n"
661 	"	-change lane C to PCIeX1\n"
662 	"lane_bank pciex2\n"
663 	"	-change lane C & lane D to PCIeX2\n"
664 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
665 );
666 #endif
667