1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ns_access.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/ls102xa_stream_id.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <fsl_esdhc.h> 18 #include <fsl_ifc.h> 19 #include <fsl_immap.h> 20 #include <netdev.h> 21 #include <fsl_mdio.h> 22 #include <tsec.h> 23 #include <fsl_sec.h> 24 #include <spl.h> 25 #include "../common/sleep.h" 26 #ifdef CONFIG_U_QE 27 #include "../../../drivers/qe/qe.h" 28 #endif 29 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define VERSION_MASK 0x00FF 34 #define BANK_MASK 0x0001 35 #define CONFIG_RESET 0x1 36 #define INIT_RESET 0x1 37 38 #define CPLD_SET_MUX_SERDES 0x20 39 #define CPLD_SET_BOOT_BANK 0x40 40 41 #define BOOT_FROM_UPPER_BANK 0x0 42 #define BOOT_FROM_LOWER_BANK 0x1 43 44 #define LANEB_SATA (0x01) 45 #define LANEB_SGMII1 (0x02) 46 #define LANEC_SGMII1 (0x04) 47 #define LANEC_PCIEX1 (0x08) 48 #define LANED_PCIEX2 (0x10) 49 #define LANED_SGMII2 (0x20) 50 51 #define MASK_LANE_B 0x1 52 #define MASK_LANE_C 0x2 53 #define MASK_LANE_D 0x4 54 #define MASK_SGMII 0x8 55 56 #define KEEP_STATUS 0x0 57 #define NEED_RESET 0x1 58 59 #define SOFT_MUX_ON_I2C3_IFC 0x2 60 #define SOFT_MUX_ON_CAN3_USB2 0x8 61 #define SOFT_MUX_ON_QE_LCD 0x10 62 63 #define PIN_I2C3_IFC_MUX_I2C3 0x0 64 #define PIN_I2C3_IFC_MUX_IFC 0x1 65 #define PIN_CAN3_USB2_MUX_USB2 0x0 66 #define PIN_CAN3_USB2_MUX_CAN3 0x1 67 #define PIN_QE_LCD_MUX_LCD 0x0 68 #define PIN_QE_LCD_MUX_QE 0x1 69 70 #ifdef CONFIG_LS102XA_NS_ACCESS 71 static struct csu_ns_dev ns_dev[] = { 72 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 73 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 74 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 75 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 76 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 77 { CSU_CSLX_GIC, CSU_ALL_RW }, 78 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 79 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 80 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 81 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 82 { CSU_CSLX_SATA, CSU_ALL_RW }, 83 { CSU_CSLX_USB3, CSU_ALL_RW }, 84 { CSU_CSLX_SERDES, CSU_ALL_RW }, 85 { CSU_CSLX_QDMA, CSU_ALL_RW }, 86 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 87 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 88 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 89 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 90 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 91 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 92 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 93 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 94 { CSU_CSLX_QSPI, CSU_ALL_RW }, 95 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 96 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 97 { CSU_CSLX_IFC, CSU_ALL_RW }, 98 { CSU_CSLX_I2C1, CSU_ALL_RW }, 99 { CSU_CSLX_USB2, CSU_ALL_RW }, 100 { CSU_CSLX_I2C3, CSU_ALL_RW }, 101 { CSU_CSLX_I2C2, CSU_ALL_RW }, 102 { CSU_CSLX_DUART2, CSU_ALL_RW }, 103 { CSU_CSLX_DUART1, CSU_ALL_RW }, 104 { CSU_CSLX_WDT2, CSU_ALL_RW }, 105 { CSU_CSLX_WDT1, CSU_ALL_RW }, 106 { CSU_CSLX_EDMA, CSU_ALL_RW }, 107 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 108 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 109 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 110 { CSU_CSLX_DDR, CSU_ALL_RW }, 111 { CSU_CSLX_QUICC, CSU_ALL_RW }, 112 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 113 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 114 { CSU_CSLX_SFP, CSU_ALL_RW }, 115 { CSU_CSLX_TMU, CSU_ALL_RW }, 116 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 117 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 118 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 119 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 120 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 121 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 122 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 123 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 124 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 125 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 126 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 127 { CSU_CSLX_CSU, CSU_ALL_RW }, 128 { CSU_CSLX_ASRC, CSU_ALL_RW }, 129 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 130 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 131 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 132 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 133 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 134 { CSU_CSLX_SAI2, CSU_ALL_RW }, 135 { CSU_CSLX_SAI1, CSU_ALL_RW }, 136 { CSU_CSLX_SAI4, CSU_ALL_RW }, 137 { CSU_CSLX_SAI3, CSU_ALL_RW }, 138 { CSU_CSLX_FTM2, CSU_ALL_RW }, 139 { CSU_CSLX_FTM1, CSU_ALL_RW }, 140 { CSU_CSLX_FTM4, CSU_ALL_RW }, 141 { CSU_CSLX_FTM3, CSU_ALL_RW }, 142 { CSU_CSLX_FTM6, CSU_ALL_RW }, 143 { CSU_CSLX_FTM5, CSU_ALL_RW }, 144 { CSU_CSLX_FTM8, CSU_ALL_RW }, 145 { CSU_CSLX_FTM7, CSU_ALL_RW }, 146 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 147 { CSU_CSLX_EPU, CSU_ALL_RW }, 148 { CSU_CSLX_GDI, CSU_ALL_RW }, 149 { CSU_CSLX_DDI, CSU_ALL_RW }, 150 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 151 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 152 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 153 }; 154 #endif 155 156 struct cpld_data { 157 u8 cpld_ver; /* cpld revision */ 158 u8 cpld_ver_sub; /* cpld sub revision */ 159 u8 pcba_ver; /* pcb revision number */ 160 u8 system_rst; /* reset system by cpld */ 161 u8 soft_mux_on; /* CPLD override physical switches Enable */ 162 u8 cfg_rcw_src1; /* Reset config word 1 */ 163 u8 cfg_rcw_src2; /* Reset config word 2 */ 164 u8 vbank; /* Flash bank selection Control */ 165 u8 gpio; /* GPIO for TWR-ELEV */ 166 u8 i2c3_ifc_mux; 167 u8 mux_spi2; 168 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 169 u8 qe_lcd_mux; /* QE and LCD Selection */ 170 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 171 u8 global_rst; /* reset with init CPLD reg to default */ 172 u8 rev1; /* Reserved */ 173 u8 rev2; /* Reserved */ 174 }; 175 176 #ifndef CONFIG_QSPI_BOOT 177 static void convert_serdes_mux(int type, int need_reset); 178 179 void cpld_show(void) 180 { 181 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 182 183 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 184 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 185 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 186 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 187 in_8(&cpld_data->vbank) & BANK_MASK); 188 189 #ifdef CONFIG_DEBUG 190 printf("soft_mux_on =%x\n", 191 in_8(&cpld_data->soft_mux_on)); 192 printf("cfg_rcw_src1 =%x\n", 193 in_8(&cpld_data->cfg_rcw_src1)); 194 printf("cfg_rcw_src2 =%x\n", 195 in_8(&cpld_data->cfg_rcw_src2)); 196 printf("vbank =%x\n", 197 in_8(&cpld_data->vbank)); 198 printf("gpio =%x\n", 199 in_8(&cpld_data->gpio)); 200 printf("i2c3_ifc_mux =%x\n", 201 in_8(&cpld_data->i2c3_ifc_mux)); 202 printf("mux_spi2 =%x\n", 203 in_8(&cpld_data->mux_spi2)); 204 printf("can3_usb2_mux =%x\n", 205 in_8(&cpld_data->can3_usb2_mux)); 206 printf("qe_lcd_mux =%x\n", 207 in_8(&cpld_data->qe_lcd_mux)); 208 printf("serdes_mux =%x\n", 209 in_8(&cpld_data->serdes_mux)); 210 #endif 211 } 212 #endif 213 214 int checkboard(void) 215 { 216 puts("Board: LS1021ATWR\n"); 217 #ifndef CONFIG_QSPI_BOOT 218 cpld_show(); 219 #endif 220 221 return 0; 222 } 223 224 unsigned int get_soc_major_rev(void) 225 { 226 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 227 unsigned int svr, major; 228 229 svr = in_be32(&gur->svr); 230 major = SVR_MAJ(svr); 231 232 return major; 233 } 234 235 void ddrmc_init(void) 236 { 237 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 238 u32 temp_sdram_cfg; 239 240 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 241 242 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 243 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 244 245 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 246 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 247 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 248 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 249 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 250 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 251 252 #ifdef CONFIG_DEEP_SLEEP 253 if (is_warm_boot()) { 254 out_be32(&ddr->sdram_cfg_2, 255 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); 256 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 257 out_be32(&ddr->init_ext_addr, (1 << 31)); 258 259 /* DRAM VRef will not be trained */ 260 out_be32(&ddr->ddr_cdr2, 261 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); 262 } else 263 #endif 264 { 265 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 266 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 267 } 268 269 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 270 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 271 272 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 273 274 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 275 276 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 277 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 278 279 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 280 281 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 282 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 283 284 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 285 udelay(1); 286 287 #ifdef CONFIG_DEEP_SLEEP 288 if (is_warm_boot()) { 289 /* enter self-refresh */ 290 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 291 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 292 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 293 294 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); 295 } else 296 #endif 297 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 298 299 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 300 301 #ifdef CONFIG_DEEP_SLEEP 302 if (is_warm_boot()) { 303 /* exit self-refresh */ 304 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 305 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 306 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 307 } 308 #endif 309 } 310 311 int dram_init(void) 312 { 313 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 314 ddrmc_init(); 315 #endif 316 317 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 318 319 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 320 fsl_dp_resume(); 321 #endif 322 323 return 0; 324 } 325 326 #ifdef CONFIG_FSL_ESDHC 327 struct fsl_esdhc_cfg esdhc_cfg[1] = { 328 {CONFIG_SYS_FSL_ESDHC_ADDR}, 329 }; 330 331 int board_mmc_init(bd_t *bis) 332 { 333 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 334 335 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 336 } 337 #endif 338 339 #ifdef CONFIG_TSEC_ENET 340 int board_eth_init(bd_t *bis) 341 { 342 struct fsl_pq_mdio_info mdio_info; 343 struct tsec_info_struct tsec_info[4]; 344 int num = 0; 345 346 #ifdef CONFIG_TSEC1 347 SET_STD_TSEC_INFO(tsec_info[num], 1); 348 if (is_serdes_configured(SGMII_TSEC1)) { 349 puts("eTSEC1 is in sgmii mode.\n"); 350 tsec_info[num].flags |= TSEC_SGMII; 351 } 352 num++; 353 #endif 354 #ifdef CONFIG_TSEC2 355 SET_STD_TSEC_INFO(tsec_info[num], 2); 356 if (is_serdes_configured(SGMII_TSEC2)) { 357 puts("eTSEC2 is in sgmii mode.\n"); 358 tsec_info[num].flags |= TSEC_SGMII; 359 } 360 num++; 361 #endif 362 #ifdef CONFIG_TSEC3 363 SET_STD_TSEC_INFO(tsec_info[num], 3); 364 num++; 365 #endif 366 if (!num) { 367 printf("No TSECs initialized\n"); 368 return 0; 369 } 370 371 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 372 mdio_info.name = DEFAULT_MII_NAME; 373 fsl_pq_mdio_init(bis, &mdio_info); 374 375 tsec_eth_init(bis, tsec_info, num); 376 377 return pci_eth_init(bis); 378 } 379 #endif 380 381 #ifndef CONFIG_QSPI_BOOT 382 int config_serdes_mux(void) 383 { 384 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 385 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 386 387 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 388 switch (protocol) { 389 case 0x10: 390 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 391 convert_serdes_mux(LANED_PCIEX2 | 392 LANEC_PCIEX1, KEEP_STATUS); 393 break; 394 case 0x20: 395 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 396 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 397 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 398 break; 399 case 0x30: 400 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 401 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 402 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 403 break; 404 case 0x70: 405 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 406 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 407 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 408 break; 409 } 410 411 return 0; 412 } 413 #endif 414 415 #ifndef CONFIG_QSPI_BOOT 416 int config_board_mux(void) 417 { 418 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 419 int conflict_flag; 420 421 conflict_flag = 0; 422 if (hwconfig("i2c3")) { 423 conflict_flag++; 424 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 425 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; 426 } 427 428 if (hwconfig("ifc")) { 429 conflict_flag++; 430 /* some signals can not enable simultaneous*/ 431 if (conflict_flag > 1) 432 goto conflict; 433 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 434 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; 435 } 436 437 conflict_flag = 0; 438 if (hwconfig("usb2")) { 439 conflict_flag++; 440 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 441 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; 442 } 443 444 if (hwconfig("can3")) { 445 conflict_flag++; 446 /* some signals can not enable simultaneous*/ 447 if (conflict_flag > 1) 448 goto conflict; 449 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 450 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; 451 } 452 453 conflict_flag = 0; 454 if (hwconfig("lcd")) { 455 conflict_flag++; 456 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 457 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; 458 } 459 460 if (hwconfig("qe")) { 461 conflict_flag++; 462 /* some signals can not enable simultaneous*/ 463 if (conflict_flag > 1) 464 goto conflict; 465 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 466 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; 467 } 468 469 return 0; 470 471 conflict: 472 printf("WARNING: pin conflict! MUX setting may failed!\n"); 473 return 0; 474 } 475 #endif 476 477 int board_early_init_f(void) 478 { 479 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 480 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 481 unsigned int major; 482 483 #ifdef CONFIG_TSEC_ENET 484 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 485 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 486 #endif 487 488 #ifdef CONFIG_FSL_IFC 489 init_early_memctl_regs(); 490 #endif 491 492 #ifdef CONFIG_FSL_DCU_FB 493 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 494 #endif 495 496 #ifdef CONFIG_FSL_QSPI 497 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 498 #endif 499 500 /* Configure Little endian for SAI, ASRC and SPDIF */ 501 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 502 503 /* 504 * Enable snoop requests and DVM message requests for 505 * Slave insterface S4 (A7 core cluster) 506 */ 507 out_le32(&cci->slave[4].snoop_ctrl, 508 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 509 510 major = get_soc_major_rev(); 511 if (major == SOC_MAJOR_VER_1_0) { 512 /* 513 * Set CCI-400 Slave interface S1, S2 Shareable Override 514 * Register All transactions are treated as non-shareable 515 */ 516 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 517 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 518 } 519 520 #if defined(CONFIG_DEEP_SLEEP) 521 if (is_warm_boot()) 522 fsl_dp_disable_console(); 523 #endif 524 525 return 0; 526 } 527 528 #ifdef CONFIG_SPL_BUILD 529 void board_init_f(ulong dummy) 530 { 531 /* Clear the BSS */ 532 memset(__bss_start, 0, __bss_end - __bss_start); 533 534 get_clocks(); 535 536 #if defined(CONFIG_DEEP_SLEEP) 537 if (is_warm_boot()) 538 fsl_dp_disable_console(); 539 #endif 540 541 preloader_console_init(); 542 543 dram_init(); 544 545 /* Allow OCRAM access permission as R/W */ 546 #ifdef CONFIG_LS102XA_NS_ACCESS 547 enable_devices_ns_access(&ns_dev[4], 1); 548 enable_devices_ns_access(&ns_dev[7], 1); 549 #endif 550 551 board_init_r(NULL, 0); 552 } 553 #endif 554 555 556 struct liodn_id_table sec_liodn_tbl[] = { 557 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 558 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 559 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 560 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 561 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 562 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 563 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 564 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 565 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 566 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 567 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 568 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 569 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 570 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 571 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 572 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 573 }; 574 575 struct smmu_stream_id dev_stream_id[] = { 576 { 0x100, 0x01, "ETSEC MAC1" }, 577 { 0x104, 0x02, "ETSEC MAC2" }, 578 { 0x108, 0x03, "ETSEC MAC3" }, 579 { 0x10c, 0x04, "PEX1" }, 580 { 0x110, 0x05, "PEX2" }, 581 { 0x114, 0x06, "qDMA" }, 582 { 0x118, 0x07, "SATA" }, 583 { 0x11c, 0x08, "USB3" }, 584 { 0x120, 0x09, "QE" }, 585 { 0x124, 0x0a, "eSDHC" }, 586 { 0x128, 0x0b, "eMA" }, 587 { 0x14c, 0x0c, "2D-ACE" }, 588 { 0x150, 0x0d, "USB2" }, 589 { 0x18c, 0x0e, "DEBUG" }, 590 }; 591 592 #ifdef CONFIG_DEEP_SLEEP 593 /* program the regulator (MC34VR500) to support deep sleep */ 594 void ls1twr_program_regulator(void) 595 { 596 unsigned int i2c_bus; 597 u8 i2c_device_id; 598 599 #define LS1TWR_I2C_BUS_MC34VR500 1 600 #define MC34VR500_ADDR 0x8 601 #define MC34VR500_DEVICEID 0x4 602 #define MC34VR500_DEVICEID_MASK 0x0f 603 604 i2c_bus = i2c_get_bus_num(); 605 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); 606 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & 607 MC34VR500_DEVICEID_MASK; 608 if (i2c_device_id != MC34VR500_DEVICEID) { 609 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); 610 return; 611 } 612 613 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); 614 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); 615 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); 616 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); 617 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); 618 619 i2c_set_bus_num(i2c_bus); 620 } 621 #endif 622 623 int board_init(void) 624 { 625 #ifndef CONFIG_SYS_FSL_NO_SERDES 626 fsl_serdes_init(); 627 #ifndef CONFIG_QSPI_BOOT 628 config_serdes_mux(); 629 #endif 630 #endif 631 632 ls1021x_config_caam_stream_id(sec_liodn_tbl, 633 ARRAY_SIZE(sec_liodn_tbl)); 634 ls102xa_config_smmu_stream_id(dev_stream_id, 635 ARRAY_SIZE(dev_stream_id)); 636 637 #ifdef CONFIG_LS102XA_NS_ACCESS 638 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 639 #endif 640 641 #ifdef CONFIG_U_QE 642 u_qe_init(); 643 #endif 644 645 #ifdef CONFIG_DEEP_SLEEP 646 ls1twr_program_regulator(); 647 #endif 648 return 0; 649 } 650 651 #if defined(CONFIG_MISC_INIT_R) 652 int misc_init_r(void) 653 { 654 #ifndef CONFIG_QSPI_BOOT 655 config_board_mux(); 656 #endif 657 658 #ifdef CONFIG_FSL_CAAM 659 return sec_init(); 660 #endif 661 } 662 #endif 663 664 #if defined(CONFIG_DEEP_SLEEP) 665 void board_sleep_prepare(void) 666 { 667 #ifdef CONFIG_LS102XA_NS_ACCESS 668 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 669 #endif 670 } 671 #endif 672 673 int ft_board_setup(void *blob, bd_t *bd) 674 { 675 ft_cpu_setup(blob, bd); 676 677 #ifdef CONFIG_PCI 678 ft_pci_setup(blob, bd); 679 #endif 680 681 return 0; 682 } 683 684 u8 flash_read8(void *addr) 685 { 686 return __raw_readb(addr + 1); 687 } 688 689 void flash_write16(u16 val, void *addr) 690 { 691 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 692 693 __raw_writew(shftval, addr); 694 } 695 696 u16 flash_read16(void *addr) 697 { 698 u16 val = __raw_readw(addr); 699 700 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 701 } 702 703 #ifndef CONFIG_QSPI_BOOT 704 static void convert_flash_bank(char bank) 705 { 706 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 707 708 printf("Now switch to boot from flash bank %d.\n", bank); 709 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 710 cpld_data->vbank = bank; 711 712 printf("Reset board to enable configuration.\n"); 713 cpld_data->system_rst = CONFIG_RESET; 714 } 715 716 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 717 char * const argv[]) 718 { 719 if (argc != 2) 720 return CMD_RET_USAGE; 721 if (strcmp(argv[1], "0") == 0) 722 convert_flash_bank(BOOT_FROM_UPPER_BANK); 723 else if (strcmp(argv[1], "1") == 0) 724 convert_flash_bank(BOOT_FROM_LOWER_BANK); 725 else 726 return CMD_RET_USAGE; 727 728 return 0; 729 } 730 731 U_BOOT_CMD( 732 boot_bank, 2, 0, flash_bank_cmd, 733 "Flash bank Selection Control", 734 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 735 ); 736 737 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 738 char * const argv[]) 739 { 740 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 741 742 if (argc > 2) 743 return CMD_RET_USAGE; 744 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 745 cpld_data->system_rst = CONFIG_RESET; 746 else if (strcmp(argv[1], "init") == 0) 747 cpld_data->global_rst = INIT_RESET; 748 else 749 return CMD_RET_USAGE; 750 751 return 0; 752 } 753 754 U_BOOT_CMD( 755 cpld_reset, 2, 0, cpld_reset_cmd, 756 "Reset via CPLD", 757 "conf\n" 758 " -reset with current CPLD configuration\n" 759 "init\n" 760 " -reset and initial CPLD configuration with default value" 761 762 ); 763 764 static void convert_serdes_mux(int type, int need_reset) 765 { 766 char current_serdes; 767 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 768 769 current_serdes = cpld_data->serdes_mux; 770 771 switch (type) { 772 case LANEB_SATA: 773 current_serdes &= ~MASK_LANE_B; 774 break; 775 case LANEB_SGMII1: 776 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 777 break; 778 case LANEC_SGMII1: 779 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 780 break; 781 case LANED_SGMII2: 782 current_serdes |= MASK_LANE_D; 783 break; 784 case LANEC_PCIEX1: 785 current_serdes |= MASK_LANE_C; 786 break; 787 case (LANED_PCIEX2 | LANEC_PCIEX1): 788 current_serdes |= MASK_LANE_C; 789 current_serdes &= ~MASK_LANE_D; 790 break; 791 default: 792 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 793 return; 794 } 795 796 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 797 cpld_data->serdes_mux = current_serdes; 798 799 if (need_reset == 1) { 800 printf("Reset board to enable configuration\n"); 801 cpld_data->system_rst = CONFIG_RESET; 802 } 803 } 804 805 void print_serdes_mux(void) 806 { 807 char current_serdes; 808 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 809 810 current_serdes = cpld_data->serdes_mux; 811 812 printf("Serdes Lane B: "); 813 if ((current_serdes & MASK_LANE_B) == 0) 814 printf("SATA,\n"); 815 else 816 printf("SGMII 1,\n"); 817 818 printf("Serdes Lane C: "); 819 if ((current_serdes & MASK_LANE_C) == 0) 820 printf("SGMII 1,\n"); 821 else 822 printf("PCIe,\n"); 823 824 printf("Serdes Lane D: "); 825 if ((current_serdes & MASK_LANE_D) == 0) 826 printf("PCIe,\n"); 827 else 828 printf("SGMII 2,\n"); 829 830 printf("SGMII 1 is on lane "); 831 if ((current_serdes & MASK_SGMII) == 0) 832 printf("C.\n"); 833 else 834 printf("B.\n"); 835 } 836 837 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 838 char * const argv[]) 839 { 840 if (argc != 2) 841 return CMD_RET_USAGE; 842 if (strcmp(argv[1], "sata") == 0) { 843 printf("Set serdes lane B to SATA.\n"); 844 convert_serdes_mux(LANEB_SATA, NEED_RESET); 845 } else if (strcmp(argv[1], "sgmii1b") == 0) { 846 printf("Set serdes lane B to SGMII 1.\n"); 847 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 848 } else if (strcmp(argv[1], "sgmii1c") == 0) { 849 printf("Set serdes lane C to SGMII 1.\n"); 850 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 851 } else if (strcmp(argv[1], "sgmii2") == 0) { 852 printf("Set serdes lane D to SGMII 2.\n"); 853 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 854 } else if (strcmp(argv[1], "pciex1") == 0) { 855 printf("Set serdes lane C to PCIe X1.\n"); 856 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 857 } else if (strcmp(argv[1], "pciex2") == 0) { 858 printf("Set serdes lane C & lane D to PCIe X2.\n"); 859 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 860 } else if (strcmp(argv[1], "show") == 0) { 861 print_serdes_mux(); 862 } else { 863 return CMD_RET_USAGE; 864 } 865 866 return 0; 867 } 868 869 U_BOOT_CMD( 870 lane_bank, 2, 0, serdes_mux_cmd, 871 "Multiplexed function setting for SerDes Lanes", 872 "sata\n" 873 " -change lane B to sata\n" 874 "lane_bank sgmii1b\n" 875 " -change lane B to SGMII1\n" 876 "lane_bank sgmii1c\n" 877 " -change lane C to SGMII1\n" 878 "lane_bank sgmii2\n" 879 " -change lane D to SGMII2\n" 880 "lane_bank pciex1\n" 881 " -change lane C to PCIeX1\n" 882 "lane_bank pciex2\n" 883 " -change lane C & lane D to PCIeX2\n" 884 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 885 ); 886 #endif 887