1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ls102xa_stream_id.h> 14 #include <asm/arch/ls102xa_devdis.h> 15 #include <asm/arch/ls102xa_soc.h> 16 #include <asm/arch/ls102xa_sata.h> 17 #include <hwconfig.h> 18 #include <mmc.h> 19 #include <fsl_csu.h> 20 #include <fsl_esdhc.h> 21 #include <fsl_ifc.h> 22 #include <fsl_immap.h> 23 #include <netdev.h> 24 #include <fsl_mdio.h> 25 #include <tsec.h> 26 #include <fsl_sec.h> 27 #include <fsl_devdis.h> 28 #include <spl.h> 29 #include "../common/sleep.h" 30 #ifdef CONFIG_U_QE 31 #include "../../../drivers/qe/qe.h" 32 #endif 33 #include <fsl_validate.h> 34 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #define VERSION_MASK 0x00FF 39 #define BANK_MASK 0x0001 40 #define CONFIG_RESET 0x1 41 #define INIT_RESET 0x1 42 43 #define CPLD_SET_MUX_SERDES 0x20 44 #define CPLD_SET_BOOT_BANK 0x40 45 46 #define BOOT_FROM_UPPER_BANK 0x0 47 #define BOOT_FROM_LOWER_BANK 0x1 48 49 #define LANEB_SATA (0x01) 50 #define LANEB_SGMII1 (0x02) 51 #define LANEC_SGMII1 (0x04) 52 #define LANEC_PCIEX1 (0x08) 53 #define LANED_PCIEX2 (0x10) 54 #define LANED_SGMII2 (0x20) 55 56 #define MASK_LANE_B 0x1 57 #define MASK_LANE_C 0x2 58 #define MASK_LANE_D 0x4 59 #define MASK_SGMII 0x8 60 61 #define KEEP_STATUS 0x0 62 #define NEED_RESET 0x1 63 64 #define SOFT_MUX_ON_I2C3_IFC 0x2 65 #define SOFT_MUX_ON_CAN3_USB2 0x8 66 #define SOFT_MUX_ON_QE_LCD 0x10 67 68 #define PIN_I2C3_IFC_MUX_I2C3 0x0 69 #define PIN_I2C3_IFC_MUX_IFC 0x1 70 #define PIN_CAN3_USB2_MUX_USB2 0x0 71 #define PIN_CAN3_USB2_MUX_CAN3 0x1 72 #define PIN_QE_LCD_MUX_LCD 0x0 73 #define PIN_QE_LCD_MUX_QE 0x1 74 75 struct cpld_data { 76 u8 cpld_ver; /* cpld revision */ 77 u8 cpld_ver_sub; /* cpld sub revision */ 78 u8 pcba_ver; /* pcb revision number */ 79 u8 system_rst; /* reset system by cpld */ 80 u8 soft_mux_on; /* CPLD override physical switches Enable */ 81 u8 cfg_rcw_src1; /* Reset config word 1 */ 82 u8 cfg_rcw_src2; /* Reset config word 2 */ 83 u8 vbank; /* Flash bank selection Control */ 84 u8 gpio; /* GPIO for TWR-ELEV */ 85 u8 i2c3_ifc_mux; 86 u8 mux_spi2; 87 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 88 u8 qe_lcd_mux; /* QE and LCD Selection */ 89 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 90 u8 global_rst; /* reset with init CPLD reg to default */ 91 u8 rev1; /* Reserved */ 92 u8 rev2; /* Reserved */ 93 }; 94 95 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 96 static void convert_serdes_mux(int type, int need_reset); 97 98 void cpld_show(void) 99 { 100 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 101 102 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 103 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 104 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 105 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 106 in_8(&cpld_data->vbank) & BANK_MASK); 107 108 #ifdef CONFIG_DEBUG 109 printf("soft_mux_on =%x\n", 110 in_8(&cpld_data->soft_mux_on)); 111 printf("cfg_rcw_src1 =%x\n", 112 in_8(&cpld_data->cfg_rcw_src1)); 113 printf("cfg_rcw_src2 =%x\n", 114 in_8(&cpld_data->cfg_rcw_src2)); 115 printf("vbank =%x\n", 116 in_8(&cpld_data->vbank)); 117 printf("gpio =%x\n", 118 in_8(&cpld_data->gpio)); 119 printf("i2c3_ifc_mux =%x\n", 120 in_8(&cpld_data->i2c3_ifc_mux)); 121 printf("mux_spi2 =%x\n", 122 in_8(&cpld_data->mux_spi2)); 123 printf("can3_usb2_mux =%x\n", 124 in_8(&cpld_data->can3_usb2_mux)); 125 printf("qe_lcd_mux =%x\n", 126 in_8(&cpld_data->qe_lcd_mux)); 127 printf("serdes_mux =%x\n", 128 in_8(&cpld_data->serdes_mux)); 129 #endif 130 } 131 #endif 132 133 int checkboard(void) 134 { 135 puts("Board: LS1021ATWR\n"); 136 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 137 cpld_show(); 138 #endif 139 140 return 0; 141 } 142 143 void ddrmc_init(void) 144 { 145 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 146 u32 temp_sdram_cfg; 147 148 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 149 150 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 151 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 152 153 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 154 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 155 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 156 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 157 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 158 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 159 160 #ifdef CONFIG_DEEP_SLEEP 161 if (is_warm_boot()) { 162 out_be32(&ddr->sdram_cfg_2, 163 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); 164 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); 165 out_be32(&ddr->init_ext_addr, (1 << 31)); 166 167 /* DRAM VRef will not be trained */ 168 out_be32(&ddr->ddr_cdr2, 169 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); 170 } else 171 #endif 172 { 173 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 174 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 175 } 176 177 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 178 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 179 180 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 181 182 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 183 184 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 185 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 186 187 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 188 189 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 190 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 191 192 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 193 udelay(1); 194 195 #ifdef CONFIG_DEEP_SLEEP 196 if (is_warm_boot()) { 197 /* enter self-refresh */ 198 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 199 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 200 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 201 202 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); 203 } else 204 #endif 205 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 206 207 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 208 209 #ifdef CONFIG_DEEP_SLEEP 210 if (is_warm_boot()) { 211 /* exit self-refresh */ 212 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); 213 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 214 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); 215 } 216 #endif 217 } 218 219 int dram_init(void) 220 { 221 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 222 ddrmc_init(); 223 #endif 224 225 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 226 227 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 228 fsl_dp_resume(); 229 #endif 230 231 return 0; 232 } 233 234 #ifdef CONFIG_FSL_ESDHC 235 struct fsl_esdhc_cfg esdhc_cfg[1] = { 236 {CONFIG_SYS_FSL_ESDHC_ADDR}, 237 }; 238 239 int board_mmc_init(bd_t *bis) 240 { 241 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 242 243 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 244 } 245 #endif 246 247 int board_eth_init(bd_t *bis) 248 { 249 #ifdef CONFIG_TSEC_ENET 250 struct fsl_pq_mdio_info mdio_info; 251 struct tsec_info_struct tsec_info[4]; 252 int num = 0; 253 254 #ifdef CONFIG_TSEC1 255 SET_STD_TSEC_INFO(tsec_info[num], 1); 256 if (is_serdes_configured(SGMII_TSEC1)) { 257 puts("eTSEC1 is in sgmii mode.\n"); 258 tsec_info[num].flags |= TSEC_SGMII; 259 } 260 num++; 261 #endif 262 #ifdef CONFIG_TSEC2 263 SET_STD_TSEC_INFO(tsec_info[num], 2); 264 if (is_serdes_configured(SGMII_TSEC2)) { 265 puts("eTSEC2 is in sgmii mode.\n"); 266 tsec_info[num].flags |= TSEC_SGMII; 267 } 268 num++; 269 #endif 270 #ifdef CONFIG_TSEC3 271 SET_STD_TSEC_INFO(tsec_info[num], 3); 272 num++; 273 #endif 274 if (!num) { 275 printf("No TSECs initialized\n"); 276 return 0; 277 } 278 279 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 280 mdio_info.name = DEFAULT_MII_NAME; 281 fsl_pq_mdio_init(bis, &mdio_info); 282 283 tsec_eth_init(bis, tsec_info, num); 284 #endif 285 286 return pci_eth_init(bis); 287 } 288 289 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 290 int config_serdes_mux(void) 291 { 292 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 293 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 294 295 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 296 switch (protocol) { 297 case 0x10: 298 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 299 convert_serdes_mux(LANED_PCIEX2 | 300 LANEC_PCIEX1, KEEP_STATUS); 301 break; 302 case 0x20: 303 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 304 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 305 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 306 break; 307 case 0x30: 308 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 309 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 310 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 311 break; 312 case 0x70: 313 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 314 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 315 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 316 break; 317 } 318 319 return 0; 320 } 321 #endif 322 323 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 324 int config_board_mux(void) 325 { 326 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 327 int conflict_flag; 328 329 conflict_flag = 0; 330 if (hwconfig("i2c3")) { 331 conflict_flag++; 332 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 333 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; 334 } 335 336 if (hwconfig("ifc")) { 337 conflict_flag++; 338 /* some signals can not enable simultaneous*/ 339 if (conflict_flag > 1) 340 goto conflict; 341 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; 342 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; 343 } 344 345 conflict_flag = 0; 346 if (hwconfig("usb2")) { 347 conflict_flag++; 348 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 349 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; 350 } 351 352 if (hwconfig("can3")) { 353 conflict_flag++; 354 /* some signals can not enable simultaneous*/ 355 if (conflict_flag > 1) 356 goto conflict; 357 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; 358 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; 359 } 360 361 conflict_flag = 0; 362 if (hwconfig("lcd")) { 363 conflict_flag++; 364 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 365 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; 366 } 367 368 if (hwconfig("qe")) { 369 conflict_flag++; 370 /* some signals can not enable simultaneous*/ 371 if (conflict_flag > 1) 372 goto conflict; 373 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; 374 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; 375 } 376 377 return 0; 378 379 conflict: 380 printf("WARNING: pin conflict! MUX setting may failed!\n"); 381 return 0; 382 } 383 #endif 384 385 int board_early_init_f(void) 386 { 387 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 388 389 #ifdef CONFIG_TSEC_ENET 390 /* clear BD & FR bits for BE BD's and frame data */ 391 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 392 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 393 #endif 394 395 #ifdef CONFIG_FSL_IFC 396 init_early_memctl_regs(); 397 #endif 398 399 arch_soc_init(); 400 401 #if defined(CONFIG_DEEP_SLEEP) 402 if (is_warm_boot()) { 403 timer_init(); 404 dram_init(); 405 } 406 #endif 407 408 return 0; 409 } 410 411 #ifdef CONFIG_SPL_BUILD 412 void board_init_f(ulong dummy) 413 { 414 void (*second_uboot)(void); 415 416 /* Clear the BSS */ 417 memset(__bss_start, 0, __bss_end - __bss_start); 418 419 get_clocks(); 420 421 #if defined(CONFIG_DEEP_SLEEP) 422 if (is_warm_boot()) 423 fsl_dp_disable_console(); 424 #endif 425 426 preloader_console_init(); 427 428 dram_init(); 429 430 /* Allow OCRAM access permission as R/W */ 431 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 432 enable_layerscape_ns_access(); 433 enable_layerscape_ns_access(); 434 #endif 435 436 /* 437 * if it is woken up from deep sleep, then jump to second 438 * stage uboot and continue executing without recopying 439 * it from SD since it has already been reserved in memeory 440 * in last boot. 441 */ 442 if (is_warm_boot()) { 443 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; 444 second_uboot(); 445 } 446 447 board_init_r(NULL, 0); 448 } 449 #endif 450 451 452 struct liodn_id_table sec_liodn_tbl[] = { 453 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 454 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 455 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 456 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 457 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 458 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 459 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 460 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 461 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 462 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 463 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 464 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 465 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 466 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 467 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 468 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 469 }; 470 471 struct smmu_stream_id dev_stream_id[] = { 472 { 0x100, 0x01, "ETSEC MAC1" }, 473 { 0x104, 0x02, "ETSEC MAC2" }, 474 { 0x108, 0x03, "ETSEC MAC3" }, 475 { 0x10c, 0x04, "PEX1" }, 476 { 0x110, 0x05, "PEX2" }, 477 { 0x114, 0x06, "qDMA" }, 478 { 0x118, 0x07, "SATA" }, 479 { 0x11c, 0x08, "USB3" }, 480 { 0x120, 0x09, "QE" }, 481 { 0x124, 0x0a, "eSDHC" }, 482 { 0x128, 0x0b, "eMA" }, 483 { 0x14c, 0x0c, "2D-ACE" }, 484 { 0x150, 0x0d, "USB2" }, 485 { 0x18c, 0x0e, "DEBUG" }, 486 }; 487 488 #ifdef CONFIG_DEEP_SLEEP 489 /* program the regulator (MC34VR500) to support deep sleep */ 490 void ls1twr_program_regulator(void) 491 { 492 unsigned int i2c_bus; 493 u8 i2c_device_id; 494 495 #define LS1TWR_I2C_BUS_MC34VR500 1 496 #define MC34VR500_ADDR 0x8 497 #define MC34VR500_DEVICEID 0x4 498 #define MC34VR500_DEVICEID_MASK 0x0f 499 500 i2c_bus = i2c_get_bus_num(); 501 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); 502 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & 503 MC34VR500_DEVICEID_MASK; 504 if (i2c_device_id != MC34VR500_DEVICEID) { 505 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); 506 return; 507 } 508 509 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); 510 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); 511 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); 512 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); 513 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); 514 515 i2c_set_bus_num(i2c_bus); 516 } 517 #endif 518 519 int board_init(void) 520 { 521 #ifndef CONFIG_SYS_FSL_NO_SERDES 522 fsl_serdes_init(); 523 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 524 config_serdes_mux(); 525 #endif 526 #endif 527 528 ls1021x_config_caam_stream_id(sec_liodn_tbl, 529 ARRAY_SIZE(sec_liodn_tbl)); 530 ls102xa_config_smmu_stream_id(dev_stream_id, 531 ARRAY_SIZE(dev_stream_id)); 532 533 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 534 enable_layerscape_ns_access(); 535 #endif 536 537 #ifdef CONFIG_U_QE 538 u_qe_init(); 539 #endif 540 541 #ifdef CONFIG_DEEP_SLEEP 542 ls1twr_program_regulator(); 543 #endif 544 return 0; 545 } 546 547 #ifdef CONFIG_BOARD_LATE_INIT 548 int board_late_init(void) 549 { 550 #ifdef CONFIG_SCSI_AHCI_PLAT 551 ls1021a_sata_init(); 552 #endif 553 #ifdef CONFIG_CHAIN_OF_TRUST 554 fsl_setenv_chain_of_trust(); 555 #endif 556 557 return 0; 558 } 559 #endif 560 561 #if defined(CONFIG_MISC_INIT_R) 562 int misc_init_r(void) 563 { 564 #ifdef CONFIG_FSL_DEVICE_DISABLE 565 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 566 #endif 567 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 568 config_board_mux(); 569 #endif 570 571 #ifdef CONFIG_FSL_CAAM 572 return sec_init(); 573 #endif 574 } 575 #endif 576 577 #if defined(CONFIG_DEEP_SLEEP) 578 void board_sleep_prepare(void) 579 { 580 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 581 enable_layerscape_ns_access(); 582 #endif 583 } 584 #endif 585 586 int ft_board_setup(void *blob, bd_t *bd) 587 { 588 ft_cpu_setup(blob, bd); 589 590 #ifdef CONFIG_PCI 591 ft_pci_setup(blob, bd); 592 #endif 593 594 return 0; 595 } 596 597 u8 flash_read8(void *addr) 598 { 599 return __raw_readb(addr + 1); 600 } 601 602 void flash_write16(u16 val, void *addr) 603 { 604 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 605 606 __raw_writew(shftval, addr); 607 } 608 609 u16 flash_read16(void *addr) 610 { 611 u16 val = __raw_readw(addr); 612 613 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 614 } 615 616 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 617 static void convert_flash_bank(char bank) 618 { 619 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 620 621 printf("Now switch to boot from flash bank %d.\n", bank); 622 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 623 cpld_data->vbank = bank; 624 625 printf("Reset board to enable configuration.\n"); 626 cpld_data->system_rst = CONFIG_RESET; 627 } 628 629 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 630 char * const argv[]) 631 { 632 if (argc != 2) 633 return CMD_RET_USAGE; 634 if (strcmp(argv[1], "0") == 0) 635 convert_flash_bank(BOOT_FROM_UPPER_BANK); 636 else if (strcmp(argv[1], "1") == 0) 637 convert_flash_bank(BOOT_FROM_LOWER_BANK); 638 else 639 return CMD_RET_USAGE; 640 641 return 0; 642 } 643 644 U_BOOT_CMD( 645 boot_bank, 2, 0, flash_bank_cmd, 646 "Flash bank Selection Control", 647 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 648 ); 649 650 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 651 char * const argv[]) 652 { 653 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 654 655 if (argc > 2) 656 return CMD_RET_USAGE; 657 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 658 cpld_data->system_rst = CONFIG_RESET; 659 else if (strcmp(argv[1], "init") == 0) 660 cpld_data->global_rst = INIT_RESET; 661 else 662 return CMD_RET_USAGE; 663 664 return 0; 665 } 666 667 U_BOOT_CMD( 668 cpld_reset, 2, 0, cpld_reset_cmd, 669 "Reset via CPLD", 670 "conf\n" 671 " -reset with current CPLD configuration\n" 672 "init\n" 673 " -reset and initial CPLD configuration with default value" 674 675 ); 676 677 static void convert_serdes_mux(int type, int need_reset) 678 { 679 char current_serdes; 680 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 681 682 current_serdes = cpld_data->serdes_mux; 683 684 switch (type) { 685 case LANEB_SATA: 686 current_serdes &= ~MASK_LANE_B; 687 break; 688 case LANEB_SGMII1: 689 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 690 break; 691 case LANEC_SGMII1: 692 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 693 break; 694 case LANED_SGMII2: 695 current_serdes |= MASK_LANE_D; 696 break; 697 case LANEC_PCIEX1: 698 current_serdes |= MASK_LANE_C; 699 break; 700 case (LANED_PCIEX2 | LANEC_PCIEX1): 701 current_serdes |= MASK_LANE_C; 702 current_serdes &= ~MASK_LANE_D; 703 break; 704 default: 705 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 706 return; 707 } 708 709 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 710 cpld_data->serdes_mux = current_serdes; 711 712 if (need_reset == 1) { 713 printf("Reset board to enable configuration\n"); 714 cpld_data->system_rst = CONFIG_RESET; 715 } 716 } 717 718 void print_serdes_mux(void) 719 { 720 char current_serdes; 721 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 722 723 current_serdes = cpld_data->serdes_mux; 724 725 printf("Serdes Lane B: "); 726 if ((current_serdes & MASK_LANE_B) == 0) 727 printf("SATA,\n"); 728 else 729 printf("SGMII 1,\n"); 730 731 printf("Serdes Lane C: "); 732 if ((current_serdes & MASK_LANE_C) == 0) 733 printf("SGMII 1,\n"); 734 else 735 printf("PCIe,\n"); 736 737 printf("Serdes Lane D: "); 738 if ((current_serdes & MASK_LANE_D) == 0) 739 printf("PCIe,\n"); 740 else 741 printf("SGMII 2,\n"); 742 743 printf("SGMII 1 is on lane "); 744 if ((current_serdes & MASK_SGMII) == 0) 745 printf("C.\n"); 746 else 747 printf("B.\n"); 748 } 749 750 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 751 char * const argv[]) 752 { 753 if (argc != 2) 754 return CMD_RET_USAGE; 755 if (strcmp(argv[1], "sata") == 0) { 756 printf("Set serdes lane B to SATA.\n"); 757 convert_serdes_mux(LANEB_SATA, NEED_RESET); 758 } else if (strcmp(argv[1], "sgmii1b") == 0) { 759 printf("Set serdes lane B to SGMII 1.\n"); 760 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 761 } else if (strcmp(argv[1], "sgmii1c") == 0) { 762 printf("Set serdes lane C to SGMII 1.\n"); 763 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 764 } else if (strcmp(argv[1], "sgmii2") == 0) { 765 printf("Set serdes lane D to SGMII 2.\n"); 766 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 767 } else if (strcmp(argv[1], "pciex1") == 0) { 768 printf("Set serdes lane C to PCIe X1.\n"); 769 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 770 } else if (strcmp(argv[1], "pciex2") == 0) { 771 printf("Set serdes lane C & lane D to PCIe X2.\n"); 772 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 773 } else if (strcmp(argv[1], "show") == 0) { 774 print_serdes_mux(); 775 } else { 776 return CMD_RET_USAGE; 777 } 778 779 return 0; 780 } 781 782 U_BOOT_CMD( 783 lane_bank, 2, 0, serdes_mux_cmd, 784 "Multiplexed function setting for SerDes Lanes", 785 "sata\n" 786 " -change lane B to sata\n" 787 "lane_bank sgmii1b\n" 788 " -change lane B to SGMII1\n" 789 "lane_bank sgmii1c\n" 790 " -change lane C to SGMII1\n" 791 "lane_bank sgmii2\n" 792 " -change lane D to SGMII2\n" 793 "lane_bank pciex1\n" 794 " -change lane C to PCIeX1\n" 795 "lane_bank pciex2\n" 796 " -change lane C & lane D to PCIeX2\n" 797 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 798 ); 799 #endif 800