1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ns_access.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/ls102xa_stream_id.h> 15 #include <asm/pcie_layerscape.h> 16 #include <mmc.h> 17 #include <fsl_esdhc.h> 18 #include <fsl_ifc.h> 19 #include <netdev.h> 20 #include <fsl_mdio.h> 21 #include <tsec.h> 22 #include <fsl_sec.h> 23 #include <spl.h> 24 #ifdef CONFIG_U_QE 25 #include "../../../drivers/qe/qe.h" 26 #endif 27 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define VERSION_MASK 0x00FF 32 #define BANK_MASK 0x0001 33 #define CONFIG_RESET 0x1 34 #define INIT_RESET 0x1 35 36 #define CPLD_SET_MUX_SERDES 0x20 37 #define CPLD_SET_BOOT_BANK 0x40 38 39 #define BOOT_FROM_UPPER_BANK 0x0 40 #define BOOT_FROM_LOWER_BANK 0x1 41 42 #define LANEB_SATA (0x01) 43 #define LANEB_SGMII1 (0x02) 44 #define LANEC_SGMII1 (0x04) 45 #define LANEC_PCIEX1 (0x08) 46 #define LANED_PCIEX2 (0x10) 47 #define LANED_SGMII2 (0x20) 48 49 #define MASK_LANE_B 0x1 50 #define MASK_LANE_C 0x2 51 #define MASK_LANE_D 0x4 52 #define MASK_SGMII 0x8 53 54 #define KEEP_STATUS 0x0 55 #define NEED_RESET 0x1 56 57 struct cpld_data { 58 u8 cpld_ver; /* cpld revision */ 59 u8 cpld_ver_sub; /* cpld sub revision */ 60 u8 pcba_ver; /* pcb revision number */ 61 u8 system_rst; /* reset system by cpld */ 62 u8 soft_mux_on; /* CPLD override physical switches Enable */ 63 u8 cfg_rcw_src1; /* Reset config word 1 */ 64 u8 cfg_rcw_src2; /* Reset config word 2 */ 65 u8 vbank; /* Flash bank selection Control */ 66 u8 gpio; /* GPIO for TWR-ELEV */ 67 u8 i2c3_ifc_mux; 68 u8 mux_spi2; 69 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ 70 u8 qe_lcd_mux; /* QE and LCD Selection */ 71 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ 72 u8 global_rst; /* reset with init CPLD reg to default */ 73 u8 rev1; /* Reserved */ 74 u8 rev2; /* Reserved */ 75 }; 76 77 #ifndef CONFIG_QSPI_BOOT 78 static void convert_serdes_mux(int type, int need_reset); 79 80 void cpld_show(void) 81 { 82 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 83 84 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", 85 in_8(&cpld_data->cpld_ver) & VERSION_MASK, 86 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, 87 in_8(&cpld_data->pcba_ver) & VERSION_MASK, 88 in_8(&cpld_data->vbank) & BANK_MASK); 89 90 #ifdef CONFIG_DEBUG 91 printf("soft_mux_on =%x\n", 92 in_8(&cpld_data->soft_mux_on)); 93 printf("cfg_rcw_src1 =%x\n", 94 in_8(&cpld_data->cfg_rcw_src1)); 95 printf("cfg_rcw_src2 =%x\n", 96 in_8(&cpld_data->cfg_rcw_src2)); 97 printf("vbank =%x\n", 98 in_8(&cpld_data->vbank)); 99 printf("gpio =%x\n", 100 in_8(&cpld_data->gpio)); 101 printf("i2c3_ifc_mux =%x\n", 102 in_8(&cpld_data->i2c3_ifc_mux)); 103 printf("mux_spi2 =%x\n", 104 in_8(&cpld_data->mux_spi2)); 105 printf("can3_usb2_mux =%x\n", 106 in_8(&cpld_data->can3_usb2_mux)); 107 printf("qe_lcd_mux =%x\n", 108 in_8(&cpld_data->qe_lcd_mux)); 109 printf("serdes_mux =%x\n", 110 in_8(&cpld_data->serdes_mux)); 111 #endif 112 } 113 #endif 114 115 int checkboard(void) 116 { 117 puts("Board: LS1021ATWR\n"); 118 #ifndef CONFIG_QSPI_BOOT 119 cpld_show(); 120 #endif 121 122 return 0; 123 } 124 125 void ddrmc_init(void) 126 { 127 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 128 129 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 130 131 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 132 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 133 134 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 135 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 136 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 137 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 138 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 139 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 140 141 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 142 143 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 144 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 145 146 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 147 148 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 149 150 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 151 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 152 153 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 154 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 155 156 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 157 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 158 159 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 160 udelay(1); 161 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN); 162 } 163 164 int dram_init(void) 165 { 166 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 167 ddrmc_init(); 168 #endif 169 170 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 171 return 0; 172 } 173 174 #ifdef CONFIG_FSL_ESDHC 175 struct fsl_esdhc_cfg esdhc_cfg[1] = { 176 {CONFIG_SYS_FSL_ESDHC_ADDR}, 177 }; 178 179 int board_mmc_init(bd_t *bis) 180 { 181 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 182 183 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 184 } 185 #endif 186 187 #ifdef CONFIG_TSEC_ENET 188 int board_eth_init(bd_t *bis) 189 { 190 struct fsl_pq_mdio_info mdio_info; 191 struct tsec_info_struct tsec_info[4]; 192 int num = 0; 193 194 #ifdef CONFIG_TSEC1 195 SET_STD_TSEC_INFO(tsec_info[num], 1); 196 if (is_serdes_configured(SGMII_TSEC1)) { 197 puts("eTSEC1 is in sgmii mode.\n"); 198 tsec_info[num].flags |= TSEC_SGMII; 199 } 200 num++; 201 #endif 202 #ifdef CONFIG_TSEC2 203 SET_STD_TSEC_INFO(tsec_info[num], 2); 204 if (is_serdes_configured(SGMII_TSEC2)) { 205 puts("eTSEC2 is in sgmii mode.\n"); 206 tsec_info[num].flags |= TSEC_SGMII; 207 } 208 num++; 209 #endif 210 #ifdef CONFIG_TSEC3 211 SET_STD_TSEC_INFO(tsec_info[num], 3); 212 num++; 213 #endif 214 if (!num) { 215 printf("No TSECs initialized\n"); 216 return 0; 217 } 218 219 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 220 mdio_info.name = DEFAULT_MII_NAME; 221 fsl_pq_mdio_init(bis, &mdio_info); 222 223 tsec_eth_init(bis, tsec_info, num); 224 225 return pci_eth_init(bis); 226 } 227 #endif 228 229 #ifndef CONFIG_QSPI_BOOT 230 int config_serdes_mux(void) 231 { 232 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 233 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 234 235 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; 236 switch (protocol) { 237 case 0x10: 238 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 239 convert_serdes_mux(LANED_PCIEX2 | 240 LANEC_PCIEX1, KEEP_STATUS); 241 break; 242 case 0x20: 243 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); 244 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 245 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 246 break; 247 case 0x30: 248 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 249 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); 250 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 251 break; 252 case 0x70: 253 convert_serdes_mux(LANEB_SATA, KEEP_STATUS); 254 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); 255 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); 256 break; 257 } 258 259 return 0; 260 } 261 #endif 262 263 int board_early_init_f(void) 264 { 265 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 266 267 #ifdef CONFIG_TSEC_ENET 268 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 269 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 270 #endif 271 272 #ifdef CONFIG_FSL_IFC 273 init_early_memctl_regs(); 274 #endif 275 276 #ifdef CONFIG_FSL_DCU_FB 277 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 278 #endif 279 280 #ifdef CONFIG_FSL_QSPI 281 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 282 #endif 283 284 return 0; 285 } 286 287 #ifdef CONFIG_SPL_BUILD 288 void board_init_f(ulong dummy) 289 { 290 /* Clear the BSS */ 291 memset(__bss_start, 0, __bss_end - __bss_start); 292 293 get_clocks(); 294 295 preloader_console_init(); 296 297 dram_init(); 298 299 board_init_r(NULL, 0); 300 } 301 #endif 302 303 #ifdef CONFIG_LS102XA_NS_ACCESS 304 static struct csu_ns_dev ns_dev[] = { 305 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 306 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 307 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 308 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 309 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 310 { CSU_CSLX_GIC, CSU_ALL_RW }, 311 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 312 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 313 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 314 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 315 { CSU_CSLX_SATA, CSU_ALL_RW }, 316 { CSU_CSLX_USB3, CSU_ALL_RW }, 317 { CSU_CSLX_SERDES, CSU_ALL_RW }, 318 { CSU_CSLX_QDMA, CSU_ALL_RW }, 319 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 320 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 321 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 322 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 323 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 324 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 325 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 326 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 327 { CSU_CSLX_QSPI, CSU_ALL_RW }, 328 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 329 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 330 { CSU_CSLX_IFC, CSU_ALL_RW }, 331 { CSU_CSLX_I2C1, CSU_ALL_RW }, 332 { CSU_CSLX_USB2, CSU_ALL_RW }, 333 { CSU_CSLX_I2C3, CSU_ALL_RW }, 334 { CSU_CSLX_I2C2, CSU_ALL_RW }, 335 { CSU_CSLX_DUART2, CSU_ALL_RW }, 336 { CSU_CSLX_DUART1, CSU_ALL_RW }, 337 { CSU_CSLX_WDT2, CSU_ALL_RW }, 338 { CSU_CSLX_WDT1, CSU_ALL_RW }, 339 { CSU_CSLX_EDMA, CSU_ALL_RW }, 340 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 341 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 342 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 343 { CSU_CSLX_DDR, CSU_ALL_RW }, 344 { CSU_CSLX_QUICC, CSU_ALL_RW }, 345 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 346 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 347 { CSU_CSLX_SFP, CSU_ALL_RW }, 348 { CSU_CSLX_TMU, CSU_ALL_RW }, 349 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 350 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 351 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 352 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 353 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 354 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 355 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 356 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 357 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 358 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 359 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 360 { CSU_CSLX_CSU, CSU_ALL_RW }, 361 { CSU_CSLX_ASRC, CSU_ALL_RW }, 362 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 363 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 364 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 365 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 366 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 367 { CSU_CSLX_SAI2, CSU_ALL_RW }, 368 { CSU_CSLX_SAI1, CSU_ALL_RW }, 369 { CSU_CSLX_SAI4, CSU_ALL_RW }, 370 { CSU_CSLX_SAI3, CSU_ALL_RW }, 371 { CSU_CSLX_FTM2, CSU_ALL_RW }, 372 { CSU_CSLX_FTM1, CSU_ALL_RW }, 373 { CSU_CSLX_FTM4, CSU_ALL_RW }, 374 { CSU_CSLX_FTM3, CSU_ALL_RW }, 375 { CSU_CSLX_FTM6, CSU_ALL_RW }, 376 { CSU_CSLX_FTM5, CSU_ALL_RW }, 377 { CSU_CSLX_FTM8, CSU_ALL_RW }, 378 { CSU_CSLX_FTM7, CSU_ALL_RW }, 379 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 380 { CSU_CSLX_EPU, CSU_ALL_RW }, 381 { CSU_CSLX_GDI, CSU_ALL_RW }, 382 { CSU_CSLX_DDI, CSU_ALL_RW }, 383 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 384 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 385 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 386 }; 387 #endif 388 389 struct smmu_stream_id dev_stream_id[] = { 390 { 0x100, 0x01, "ETSEC MAC1" }, 391 { 0x104, 0x02, "ETSEC MAC2" }, 392 { 0x108, 0x03, "ETSEC MAC3" }, 393 { 0x10c, 0x04, "PEX1" }, 394 { 0x110, 0x05, "PEX2" }, 395 { 0x114, 0x06, "qDMA" }, 396 { 0x118, 0x07, "SATA" }, 397 { 0x11c, 0x08, "USB3" }, 398 { 0x120, 0x09, "QE" }, 399 { 0x124, 0x0a, "eSDHC" }, 400 { 0x128, 0x0b, "eMA" }, 401 { 0x14c, 0x0c, "2D-ACE" }, 402 { 0x150, 0x0d, "USB2" }, 403 { 0x18c, 0x0e, "DEBUG" }, 404 }; 405 406 int board_init(void) 407 { 408 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 409 410 /* 411 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register 412 * All transactions are treated as non-shareable 413 */ 414 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 415 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 416 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 417 418 #ifndef CONFIG_SYS_FSL_NO_SERDES 419 fsl_serdes_init(); 420 #ifndef CONFIG_QSPI_BOOT 421 config_serdes_mux(); 422 #endif 423 #endif 424 425 ls102xa_config_smmu_stream_id(dev_stream_id, 426 ARRAY_SIZE(dev_stream_id)); 427 428 #ifdef CONFIG_LS102XA_NS_ACCESS 429 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 430 #endif 431 432 #ifdef CONFIG_U_QE 433 u_qe_init(); 434 #endif 435 436 return 0; 437 } 438 439 #if defined(CONFIG_MISC_INIT_R) 440 int misc_init_r(void) 441 { 442 #ifdef CONFIG_FSL_CAAM 443 return sec_init(); 444 #endif 445 } 446 #endif 447 448 int ft_board_setup(void *blob, bd_t *bd) 449 { 450 ft_cpu_setup(blob, bd); 451 452 #ifdef CONFIG_PCIE_LAYERSCAPE 453 ft_pcie_setup(blob, bd); 454 #endif 455 456 return 0; 457 } 458 459 u8 flash_read8(void *addr) 460 { 461 return __raw_readb(addr + 1); 462 } 463 464 void flash_write16(u16 val, void *addr) 465 { 466 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 467 468 __raw_writew(shftval, addr); 469 } 470 471 u16 flash_read16(void *addr) 472 { 473 u16 val = __raw_readw(addr); 474 475 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 476 } 477 478 #ifndef CONFIG_QSPI_BOOT 479 static void convert_flash_bank(char bank) 480 { 481 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 482 483 printf("Now switch to boot from flash bank %d.\n", bank); 484 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; 485 cpld_data->vbank = bank; 486 487 printf("Reset board to enable configuration.\n"); 488 cpld_data->system_rst = CONFIG_RESET; 489 } 490 491 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 492 char * const argv[]) 493 { 494 if (argc != 2) 495 return CMD_RET_USAGE; 496 if (strcmp(argv[1], "0") == 0) 497 convert_flash_bank(BOOT_FROM_UPPER_BANK); 498 else if (strcmp(argv[1], "1") == 0) 499 convert_flash_bank(BOOT_FROM_LOWER_BANK); 500 else 501 return CMD_RET_USAGE; 502 503 return 0; 504 } 505 506 U_BOOT_CMD( 507 boot_bank, 2, 0, flash_bank_cmd, 508 "Flash bank Selection Control", 509 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" 510 ); 511 512 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 513 char * const argv[]) 514 { 515 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 516 517 if (argc > 2) 518 return CMD_RET_USAGE; 519 if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) 520 cpld_data->system_rst = CONFIG_RESET; 521 else if (strcmp(argv[1], "init") == 0) 522 cpld_data->global_rst = INIT_RESET; 523 else 524 return CMD_RET_USAGE; 525 526 return 0; 527 } 528 529 U_BOOT_CMD( 530 cpld_reset, 2, 0, cpld_reset_cmd, 531 "Reset via CPLD", 532 "conf\n" 533 " -reset with current CPLD configuration\n" 534 "init\n" 535 " -reset and initial CPLD configuration with default value" 536 537 ); 538 539 static void convert_serdes_mux(int type, int need_reset) 540 { 541 char current_serdes; 542 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 543 544 current_serdes = cpld_data->serdes_mux; 545 546 switch (type) { 547 case LANEB_SATA: 548 current_serdes &= ~MASK_LANE_B; 549 break; 550 case LANEB_SGMII1: 551 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 552 break; 553 case LANEC_SGMII1: 554 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); 555 break; 556 case LANED_SGMII2: 557 current_serdes |= MASK_LANE_D; 558 break; 559 case LANEC_PCIEX1: 560 current_serdes |= MASK_LANE_C; 561 break; 562 case (LANED_PCIEX2 | LANEC_PCIEX1): 563 current_serdes |= MASK_LANE_C; 564 current_serdes &= ~MASK_LANE_D; 565 break; 566 default: 567 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); 568 return; 569 } 570 571 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; 572 cpld_data->serdes_mux = current_serdes; 573 574 if (need_reset == 1) { 575 printf("Reset board to enable configuration\n"); 576 cpld_data->system_rst = CONFIG_RESET; 577 } 578 } 579 580 void print_serdes_mux(void) 581 { 582 char current_serdes; 583 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); 584 585 current_serdes = cpld_data->serdes_mux; 586 587 printf("Serdes Lane B: "); 588 if ((current_serdes & MASK_LANE_B) == 0) 589 printf("SATA,\n"); 590 else 591 printf("SGMII 1,\n"); 592 593 printf("Serdes Lane C: "); 594 if ((current_serdes & MASK_LANE_C) == 0) 595 printf("SGMII 1,\n"); 596 else 597 printf("PCIe,\n"); 598 599 printf("Serdes Lane D: "); 600 if ((current_serdes & MASK_LANE_D) == 0) 601 printf("PCIe,\n"); 602 else 603 printf("SGMII 2,\n"); 604 605 printf("SGMII 1 is on lane "); 606 if ((current_serdes & MASK_SGMII) == 0) 607 printf("C.\n"); 608 else 609 printf("B.\n"); 610 } 611 612 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, 613 char * const argv[]) 614 { 615 if (argc != 2) 616 return CMD_RET_USAGE; 617 if (strcmp(argv[1], "sata") == 0) { 618 printf("Set serdes lane B to SATA.\n"); 619 convert_serdes_mux(LANEB_SATA, NEED_RESET); 620 } else if (strcmp(argv[1], "sgmii1b") == 0) { 621 printf("Set serdes lane B to SGMII 1.\n"); 622 convert_serdes_mux(LANEB_SGMII1, NEED_RESET); 623 } else if (strcmp(argv[1], "sgmii1c") == 0) { 624 printf("Set serdes lane C to SGMII 1.\n"); 625 convert_serdes_mux(LANEC_SGMII1, NEED_RESET); 626 } else if (strcmp(argv[1], "sgmii2") == 0) { 627 printf("Set serdes lane D to SGMII 2.\n"); 628 convert_serdes_mux(LANED_SGMII2, NEED_RESET); 629 } else if (strcmp(argv[1], "pciex1") == 0) { 630 printf("Set serdes lane C to PCIe X1.\n"); 631 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); 632 } else if (strcmp(argv[1], "pciex2") == 0) { 633 printf("Set serdes lane C & lane D to PCIe X2.\n"); 634 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); 635 } else if (strcmp(argv[1], "show") == 0) { 636 print_serdes_mux(); 637 } else { 638 return CMD_RET_USAGE; 639 } 640 641 return 0; 642 } 643 644 U_BOOT_CMD( 645 lane_bank, 2, 0, serdes_mux_cmd, 646 "Multiplexed function setting for SerDes Lanes", 647 "sata\n" 648 " -change lane B to sata\n" 649 "lane_bank sgmii1b\n" 650 " -change lane B to SGMII1\n" 651 "lane_bank sgmii1c\n" 652 " -change lane C to SGMII1\n" 653 "lane_bank sgmii2\n" 654 " -change lane D to SGMII2\n" 655 "lane_bank pciex1\n" 656 " -change lane C to PCIeX1\n" 657 "lane_bank pciex2\n" 658 " -change lane C & lane D to PCIeX2\n" 659 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" 660 ); 661 #endif 662