1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_soc.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_csu.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_sec.h>
22 #include <spl.h>
23 #include <fsl_devdis.h>
24 #include <fsl_validate.h>
25 #include <fsl_ddr.h>
26 #include "../common/sleep.h"
27 #include "../common/qixis.h"
28 #include "ls1021aqds_qixis.h"
29 #ifdef CONFIG_U_QE
30 #include <fsl_qe.h>
31 #endif
32 
33 #define PIN_MUX_SEL_CAN		0x03
34 #define PIN_MUX_SEL_IIC2	0xa0
35 #define PIN_MUX_SEL_RGMII	0x00
36 #define PIN_MUX_SEL_SAI		0x0c
37 #define PIN_MUX_SEL_SDHC	0x00
38 
39 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
40 #define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
41 enum {
42 	MUX_TYPE_CAN,
43 	MUX_TYPE_IIC2,
44 	MUX_TYPE_RGMII,
45 	MUX_TYPE_SAI,
46 	MUX_TYPE_SDHC,
47 	MUX_TYPE_SD_PCI4,
48 	MUX_TYPE_SD_PC_SA_SG_SG,
49 	MUX_TYPE_SD_PC_SA_PC_SG,
50 	MUX_TYPE_SD_PC_SG_SG,
51 };
52 
53 enum {
54 	GE0_CLK125,
55 	GE2_CLK125,
56 	GE1_CLK125,
57 };
58 
59 int checkboard(void)
60 {
61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
62 	char buf[64];
63 #endif
64 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
65 	u8 sw;
66 #endif
67 
68 	puts("Board: LS1021AQDS\n");
69 
70 #ifdef CONFIG_SD_BOOT
71 	puts("SD\n");
72 #elif CONFIG_QSPI_BOOT
73 	puts("QSPI\n");
74 #else
75 	sw = QIXIS_READ(brdcfg[0]);
76 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
77 
78 	if (sw < 0x8)
79 		printf("vBank: %d\n", sw);
80 	else if (sw == 0x8)
81 		puts("PromJet\n");
82 	else if (sw == 0x9)
83 		puts("NAND\n");
84 	else if (sw == 0x15)
85 		printf("IFCCard\n");
86 	else
87 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
88 #endif
89 
90 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
91 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
92 	       QIXIS_READ(id), QIXIS_READ(arch));
93 
94 	printf("FPGA:  v%d (%s), build %d\n",
95 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
96 	       (int)qixis_read_minor());
97 #endif
98 
99 	return 0;
100 }
101 
102 unsigned long get_board_sys_clk(void)
103 {
104 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
105 
106 	switch (sysclk_conf & 0x0f) {
107 	case QIXIS_SYSCLK_64:
108 		return 64000000;
109 	case QIXIS_SYSCLK_83:
110 		return 83333333;
111 	case QIXIS_SYSCLK_100:
112 		return 100000000;
113 	case QIXIS_SYSCLK_125:
114 		return 125000000;
115 	case QIXIS_SYSCLK_133:
116 		return 133333333;
117 	case QIXIS_SYSCLK_150:
118 		return 150000000;
119 	case QIXIS_SYSCLK_160:
120 		return 160000000;
121 	case QIXIS_SYSCLK_166:
122 		return 166666666;
123 	}
124 	return 66666666;
125 }
126 
127 unsigned long get_board_ddr_clk(void)
128 {
129 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
130 
131 	switch ((ddrclk_conf & 0x30) >> 4) {
132 	case QIXIS_DDRCLK_100:
133 		return 100000000;
134 	case QIXIS_DDRCLK_125:
135 		return 125000000;
136 	case QIXIS_DDRCLK_133:
137 		return 133333333;
138 	}
139 	return 66666666;
140 }
141 
142 int select_i2c_ch_pca9547(u8 ch)
143 {
144 	int ret;
145 
146 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
147 	if (ret) {
148 		puts("PCA: failed to select proper channel\n");
149 		return ret;
150 	}
151 
152 	return 0;
153 }
154 
155 int dram_init(void)
156 {
157 	/*
158 	 * When resuming from deep sleep, the I2C channel may not be
159 	 * in the default channel. So, switch to the default channel
160 	 * before accessing DDR SPD.
161 	 */
162 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
163 	return fsl_initdram();
164 }
165 
166 #ifdef CONFIG_FSL_ESDHC
167 struct fsl_esdhc_cfg esdhc_cfg[1] = {
168 	{CONFIG_SYS_FSL_ESDHC_ADDR},
169 };
170 
171 int board_mmc_init(bd_t *bis)
172 {
173 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
174 
175 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
176 }
177 #endif
178 
179 int board_early_init_f(void)
180 {
181 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
182 
183 #ifdef CONFIG_TSEC_ENET
184 	/* clear BD & FR bits for BE BD's and frame data */
185 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
186 #endif
187 
188 #ifdef CONFIG_FSL_IFC
189 	init_early_memctl_regs();
190 #endif
191 
192 	arch_soc_init();
193 
194 #if defined(CONFIG_DEEP_SLEEP)
195 	if (is_warm_boot())
196 		fsl_dp_disable_console();
197 #endif
198 
199 	return 0;
200 }
201 
202 #ifdef CONFIG_SPL_BUILD
203 void board_init_f(ulong dummy)
204 {
205 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
206 					CONFIG_SYS_CCI400_OFFSET);
207 	unsigned int major;
208 
209 #ifdef CONFIG_NAND_BOOT
210 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
211 	u32 porsr1, pinctl;
212 
213 	/*
214 	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
215 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
216 	 * This workaround changes RCW source to make all signals enabled.
217 	 */
218 	porsr1 = in_be32(&gur->porsr1);
219 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
220 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
221 	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
222 		 pinctl);
223 #endif
224 
225 	/* Clear the BSS */
226 	memset(__bss_start, 0, __bss_end - __bss_start);
227 
228 #ifdef CONFIG_FSL_IFC
229 	init_early_memctl_regs();
230 #endif
231 
232 	get_clocks();
233 
234 #if defined(CONFIG_DEEP_SLEEP)
235 	if (is_warm_boot())
236 		fsl_dp_disable_console();
237 #endif
238 
239 	preloader_console_init();
240 
241 #ifdef CONFIG_SPL_I2C_SUPPORT
242 	i2c_init_all();
243 #endif
244 
245 	major = get_soc_major_rev();
246 	if (major == SOC_MAJOR_VER_1_0)
247 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
248 
249 	dram_init();
250 
251 	/* Allow OCRAM access permission as R/W */
252 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
253 	enable_layerscape_ns_access();
254 #endif
255 
256 	board_init_r(NULL, 0);
257 }
258 #endif
259 
260 void config_etseccm_source(int etsec_gtx_125_mux)
261 {
262 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
263 
264 	switch (etsec_gtx_125_mux) {
265 	case GE0_CLK125:
266 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
267 		debug("etseccm set to GE0_CLK125\n");
268 		break;
269 
270 	case GE2_CLK125:
271 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
272 		debug("etseccm set to GE2_CLK125\n");
273 		break;
274 
275 	case GE1_CLK125:
276 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
277 		debug("etseccm set to GE1_CLK125\n");
278 		break;
279 
280 	default:
281 		printf("Error! trying to set etseccm to invalid value\n");
282 		break;
283 	}
284 }
285 
286 int config_board_mux(int ctrl_type)
287 {
288 	u8 reg12, reg14;
289 
290 	reg12 = QIXIS_READ(brdcfg[12]);
291 	reg14 = QIXIS_READ(brdcfg[14]);
292 
293 	switch (ctrl_type) {
294 	case MUX_TYPE_CAN:
295 		config_etseccm_source(GE2_CLK125);
296 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
297 		break;
298 	case MUX_TYPE_IIC2:
299 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
300 		break;
301 	case MUX_TYPE_RGMII:
302 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
303 		break;
304 	case MUX_TYPE_SAI:
305 		config_etseccm_source(GE2_CLK125);
306 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
307 		break;
308 	case MUX_TYPE_SDHC:
309 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
310 		break;
311 	case MUX_TYPE_SD_PCI4:
312 		reg12 = 0x38;
313 		break;
314 	case MUX_TYPE_SD_PC_SA_SG_SG:
315 		reg12 = 0x01;
316 		break;
317 	case MUX_TYPE_SD_PC_SA_PC_SG:
318 		reg12 = 0x01;
319 		break;
320 	case MUX_TYPE_SD_PC_SG_SG:
321 		reg12 = 0x21;
322 		break;
323 	default:
324 		printf("Wrong mux interface type\n");
325 		return -1;
326 	}
327 
328 	QIXIS_WRITE(brdcfg[12], reg12);
329 	QIXIS_WRITE(brdcfg[14], reg14);
330 
331 	return 0;
332 }
333 
334 int config_serdes_mux(void)
335 {
336 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
337 	u32 cfg;
338 
339 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
340 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
341 
342 	switch (cfg) {
343 	case 0x0:
344 		config_board_mux(MUX_TYPE_SD_PCI4);
345 		break;
346 	case 0x30:
347 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
348 		break;
349 	case 0x60:
350 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
351 		break;
352 	case 0x70:
353 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
354 		break;
355 	default:
356 		printf("SRDS1 prtcl:0x%x\n", cfg);
357 		break;
358 	}
359 
360 	return 0;
361 }
362 
363 #ifdef CONFIG_BOARD_LATE_INIT
364 int board_late_init(void)
365 {
366 #ifdef CONFIG_SCSI_AHCI_PLAT
367 	ls1021a_sata_init();
368 #endif
369 #ifdef CONFIG_CHAIN_OF_TRUST
370 	fsl_setenv_chain_of_trust();
371 #endif
372 
373 	return 0;
374 }
375 #endif
376 
377 int misc_init_r(void)
378 {
379 	int conflict_flag;
380 
381 	/* some signals can not enable simultaneous*/
382 	conflict_flag = 0;
383 	if (hwconfig("sdhc"))
384 		conflict_flag++;
385 	if (hwconfig("iic2"))
386 		conflict_flag++;
387 	if (conflict_flag > 1) {
388 		printf("WARNING: pin conflict !\n");
389 		return 0;
390 	}
391 
392 	conflict_flag = 0;
393 	if (hwconfig("rgmii"))
394 		conflict_flag++;
395 	if (hwconfig("can"))
396 		conflict_flag++;
397 	if (hwconfig("sai"))
398 		conflict_flag++;
399 	if (conflict_flag > 1) {
400 		printf("WARNING: pin conflict !\n");
401 		return 0;
402 	}
403 
404 	if (hwconfig("can"))
405 		config_board_mux(MUX_TYPE_CAN);
406 	else if (hwconfig("rgmii"))
407 		config_board_mux(MUX_TYPE_RGMII);
408 	else if (hwconfig("sai"))
409 		config_board_mux(MUX_TYPE_SAI);
410 
411 	if (hwconfig("iic2"))
412 		config_board_mux(MUX_TYPE_IIC2);
413 	else if (hwconfig("sdhc"))
414 		config_board_mux(MUX_TYPE_SDHC);
415 
416 #ifdef CONFIG_FSL_DEVICE_DISABLE
417 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
418 #endif
419 #ifdef CONFIG_FSL_CAAM
420 	return sec_init();
421 #endif
422 	return 0;
423 }
424 
425 int board_init(void)
426 {
427 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
428 					CONFIG_SYS_CCI400_OFFSET);
429 	unsigned int major;
430 
431 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
432 	erratum_a010315();
433 #endif
434 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
435 	erratum_a009942_check_cpo();
436 #endif
437 	major = get_soc_major_rev();
438 	if (major == SOC_MAJOR_VER_1_0) {
439 		/* Set CCI-400 control override register to
440 		 * enable barrier transaction */
441 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
442 	}
443 
444 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
445 
446 #ifndef CONFIG_SYS_FSL_NO_SERDES
447 	fsl_serdes_init();
448 	config_serdes_mux();
449 #endif
450 
451 	ls102xa_smmu_stream_id_init();
452 
453 #ifdef CONFIG_U_QE
454 	u_qe_init();
455 #endif
456 
457 	return 0;
458 }
459 
460 #if defined(CONFIG_DEEP_SLEEP)
461 void board_sleep_prepare(void)
462 {
463 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
464 						CONFIG_SYS_CCI400_OFFSET);
465 	unsigned int major;
466 
467 	major = get_soc_major_rev();
468 	if (major == SOC_MAJOR_VER_1_0) {
469 		/* Set CCI-400 control override register to
470 		 * enable barrier transaction */
471 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
472 	}
473 
474 
475 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
476 	enable_layerscape_ns_access();
477 #endif
478 }
479 #endif
480 
481 int ft_board_setup(void *blob, bd_t *bd)
482 {
483 	ft_cpu_setup(blob, bd);
484 
485 #ifdef CONFIG_PCI
486 	ft_pci_setup(blob, bd);
487 #endif
488 
489 	return 0;
490 }
491 
492 u8 flash_read8(void *addr)
493 {
494 	return __raw_readb(addr + 1);
495 }
496 
497 void flash_write16(u16 val, void *addr)
498 {
499 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
500 
501 	__raw_writew(shftval, addr);
502 }
503 
504 u16 flash_read16(void *addr)
505 {
506 	u16 val = __raw_readw(addr);
507 
508 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
509 }
510