1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_stream_id.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_csu.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_sec.h>
22 #include <spl.h>
23 #include <fsl_devdis.h>
24 
25 #include "../common/sleep.h"
26 #include "../common/qixis.h"
27 #include "ls1021aqds_qixis.h"
28 #ifdef CONFIG_U_QE
29 #include "../../../drivers/qe/qe.h"
30 #endif
31 
32 #define PIN_MUX_SEL_CAN		0x03
33 #define PIN_MUX_SEL_IIC2	0xa0
34 #define PIN_MUX_SEL_RGMII	0x00
35 #define PIN_MUX_SEL_SAI		0x0c
36 #define PIN_MUX_SEL_SDHC	0x00
37 
38 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
39 #define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 enum {
43 	MUX_TYPE_CAN,
44 	MUX_TYPE_IIC2,
45 	MUX_TYPE_RGMII,
46 	MUX_TYPE_SAI,
47 	MUX_TYPE_SDHC,
48 	MUX_TYPE_SD_PCI4,
49 	MUX_TYPE_SD_PC_SA_SG_SG,
50 	MUX_TYPE_SD_PC_SA_PC_SG,
51 	MUX_TYPE_SD_PC_SG_SG,
52 };
53 
54 enum {
55 	GE0_CLK125,
56 	GE2_CLK125,
57 	GE1_CLK125,
58 };
59 
60 int checkboard(void)
61 {
62 #ifndef CONFIG_QSPI_BOOT
63 	char buf[64];
64 #endif
65 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
66 	u8 sw;
67 #endif
68 
69 	puts("Board: LS1021AQDS\n");
70 
71 #ifdef CONFIG_SD_BOOT
72 	puts("SD\n");
73 #elif CONFIG_QSPI_BOOT
74 	puts("QSPI\n");
75 #else
76 	sw = QIXIS_READ(brdcfg[0]);
77 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
78 
79 	if (sw < 0x8)
80 		printf("vBank: %d\n", sw);
81 	else if (sw == 0x8)
82 		puts("PromJet\n");
83 	else if (sw == 0x9)
84 		puts("NAND\n");
85 	else if (sw == 0x15)
86 		printf("IFCCard\n");
87 	else
88 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
89 #endif
90 
91 #ifndef CONFIG_QSPI_BOOT
92 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
93 	       QIXIS_READ(id), QIXIS_READ(arch));
94 
95 	printf("FPGA:  v%d (%s), build %d\n",
96 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
97 	       (int)qixis_read_minor());
98 #endif
99 
100 	return 0;
101 }
102 
103 unsigned long get_board_sys_clk(void)
104 {
105 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
106 
107 	switch (sysclk_conf & 0x0f) {
108 	case QIXIS_SYSCLK_64:
109 		return 64000000;
110 	case QIXIS_SYSCLK_83:
111 		return 83333333;
112 	case QIXIS_SYSCLK_100:
113 		return 100000000;
114 	case QIXIS_SYSCLK_125:
115 		return 125000000;
116 	case QIXIS_SYSCLK_133:
117 		return 133333333;
118 	case QIXIS_SYSCLK_150:
119 		return 150000000;
120 	case QIXIS_SYSCLK_160:
121 		return 160000000;
122 	case QIXIS_SYSCLK_166:
123 		return 166666666;
124 	}
125 	return 66666666;
126 }
127 
128 unsigned long get_board_ddr_clk(void)
129 {
130 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
131 
132 	switch ((ddrclk_conf & 0x30) >> 4) {
133 	case QIXIS_DDRCLK_100:
134 		return 100000000;
135 	case QIXIS_DDRCLK_125:
136 		return 125000000;
137 	case QIXIS_DDRCLK_133:
138 		return 133333333;
139 	}
140 	return 66666666;
141 }
142 
143 unsigned int get_soc_major_rev(void)
144 {
145 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
146 	unsigned int svr, major;
147 
148 	svr = in_be32(&gur->svr);
149 	major = SVR_MAJ(svr);
150 
151 	return major;
152 }
153 
154 int select_i2c_ch_pca9547(u8 ch)
155 {
156 	int ret;
157 
158 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
159 	if (ret) {
160 		puts("PCA: failed to select proper channel\n");
161 		return ret;
162 	}
163 
164 	return 0;
165 }
166 
167 int dram_init(void)
168 {
169 	/*
170 	 * When resuming from deep sleep, the I2C channel may not be
171 	 * in the default channel. So, switch to the default channel
172 	 * before accessing DDR SPD.
173 	 */
174 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
175 	gd->ram_size = initdram(0);
176 
177 	return 0;
178 }
179 
180 #ifdef CONFIG_FSL_ESDHC
181 struct fsl_esdhc_cfg esdhc_cfg[1] = {
182 	{CONFIG_SYS_FSL_ESDHC_ADDR},
183 };
184 
185 int board_mmc_init(bd_t *bis)
186 {
187 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
188 
189 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
190 }
191 #endif
192 
193 int board_early_init_f(void)
194 {
195 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
196 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
197 	unsigned int major;
198 
199 #ifdef CONFIG_TSEC_ENET
200 	/* clear BD & FR bits for BE BD's and frame data */
201 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
202 #endif
203 
204 #ifdef CONFIG_FSL_IFC
205 	init_early_memctl_regs();
206 #endif
207 
208 #ifdef CONFIG_FSL_QSPI
209 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
210 #endif
211 
212 #ifdef CONFIG_FSL_DCU_FB
213 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
214 #endif
215 
216 	/* Configure Little endian for SAI, ASRC and SPDIF */
217 	out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
218 
219 	/*
220 	 * Enable snoop requests and DVM message requests for
221 	 * Slave insterface S4 (A7 core cluster)
222 	 */
223 	out_le32(&cci->slave[4].snoop_ctrl,
224 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
225 
226 	major = get_soc_major_rev();
227 	if (major == SOC_MAJOR_VER_1_0) {
228 		/*
229 		 * Set CCI-400 Slave interface S1, S2 Shareable Override
230 		 * Register All transactions are treated as non-shareable
231 		 */
232 		out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
233 		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
234 
235 		/* Workaround for the issue that DDR could not respond to
236 		 * barrier transaction which is generated by executing DSB/ISB
237 		 * instruction. Set CCI-400 control override register to
238 		 * terminate the barrier transaction. After DDR is initialized,
239 		 * allow barrier transaction to DDR again */
240 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
241 	}
242 
243 #if defined(CONFIG_DEEP_SLEEP)
244 	if (is_warm_boot())
245 		fsl_dp_disable_console();
246 #endif
247 
248 	return 0;
249 }
250 
251 #ifdef CONFIG_SPL_BUILD
252 void board_init_f(ulong dummy)
253 {
254 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
255 	unsigned int major;
256 
257 #ifdef CONFIG_NAND_BOOT
258 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
259 	u32 porsr1, pinctl;
260 
261 	/*
262 	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
263 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
264 	 * This workaround changes RCW source to make all signals enabled.
265 	 */
266 	porsr1 = in_be32(&gur->porsr1);
267 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
268 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
269 	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
270 		 pinctl);
271 #endif
272 
273 	/* Clear the BSS */
274 	memset(__bss_start, 0, __bss_end - __bss_start);
275 
276 #ifdef CONFIG_FSL_IFC
277 	init_early_memctl_regs();
278 #endif
279 
280 	get_clocks();
281 
282 #if defined(CONFIG_DEEP_SLEEP)
283 	if (is_warm_boot())
284 		fsl_dp_disable_console();
285 #endif
286 
287 	preloader_console_init();
288 
289 #ifdef CONFIG_SPL_I2C_SUPPORT
290 	i2c_init_all();
291 #endif
292 
293 	major = get_soc_major_rev();
294 	if (major == SOC_MAJOR_VER_1_0)
295 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
296 
297 	dram_init();
298 
299 	/* Allow OCRAM access permission as R/W */
300 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
301 	enable_layerscape_ns_access();
302 #endif
303 
304 	board_init_r(NULL, 0);
305 }
306 #endif
307 
308 void config_etseccm_source(int etsec_gtx_125_mux)
309 {
310 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
311 
312 	switch (etsec_gtx_125_mux) {
313 	case GE0_CLK125:
314 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
315 		debug("etseccm set to GE0_CLK125\n");
316 		break;
317 
318 	case GE2_CLK125:
319 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
320 		debug("etseccm set to GE2_CLK125\n");
321 		break;
322 
323 	case GE1_CLK125:
324 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
325 		debug("etseccm set to GE1_CLK125\n");
326 		break;
327 
328 	default:
329 		printf("Error! trying to set etseccm to invalid value\n");
330 		break;
331 	}
332 }
333 
334 int config_board_mux(int ctrl_type)
335 {
336 	u8 reg12, reg14;
337 
338 	reg12 = QIXIS_READ(brdcfg[12]);
339 	reg14 = QIXIS_READ(brdcfg[14]);
340 
341 	switch (ctrl_type) {
342 	case MUX_TYPE_CAN:
343 		config_etseccm_source(GE2_CLK125);
344 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
345 		break;
346 	case MUX_TYPE_IIC2:
347 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
348 		break;
349 	case MUX_TYPE_RGMII:
350 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
351 		break;
352 	case MUX_TYPE_SAI:
353 		config_etseccm_source(GE2_CLK125);
354 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
355 		break;
356 	case MUX_TYPE_SDHC:
357 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
358 		break;
359 	case MUX_TYPE_SD_PCI4:
360 		reg12 = 0x38;
361 		break;
362 	case MUX_TYPE_SD_PC_SA_SG_SG:
363 		reg12 = 0x01;
364 		break;
365 	case MUX_TYPE_SD_PC_SA_PC_SG:
366 		reg12 = 0x01;
367 		break;
368 	case MUX_TYPE_SD_PC_SG_SG:
369 		reg12 = 0x21;
370 		break;
371 	default:
372 		printf("Wrong mux interface type\n");
373 		return -1;
374 	}
375 
376 	QIXIS_WRITE(brdcfg[12], reg12);
377 	QIXIS_WRITE(brdcfg[14], reg14);
378 
379 	return 0;
380 }
381 
382 int config_serdes_mux(void)
383 {
384 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
385 	u32 cfg;
386 
387 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
388 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
389 
390 	switch (cfg) {
391 	case 0x0:
392 		config_board_mux(MUX_TYPE_SD_PCI4);
393 		break;
394 	case 0x30:
395 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
396 		break;
397 	case 0x60:
398 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
399 		break;
400 	case 0x70:
401 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
402 		break;
403 	default:
404 		printf("SRDS1 prtcl:0x%x\n", cfg);
405 		break;
406 	}
407 
408 	return 0;
409 }
410 
411 #ifdef CONFIG_BOARD_LATE_INIT
412 int board_late_init(void)
413 {
414 #ifdef CONFIG_SCSI_AHCI_PLAT
415 	ls1021a_sata_init();
416 #endif
417 
418 	return 0;
419 }
420 #endif
421 
422 int misc_init_r(void)
423 {
424 	int conflict_flag;
425 
426 	/* some signals can not enable simultaneous*/
427 	conflict_flag = 0;
428 	if (hwconfig("sdhc"))
429 		conflict_flag++;
430 	if (hwconfig("iic2"))
431 		conflict_flag++;
432 	if (conflict_flag > 1) {
433 		printf("WARNING: pin conflict !\n");
434 		return 0;
435 	}
436 
437 	conflict_flag = 0;
438 	if (hwconfig("rgmii"))
439 		conflict_flag++;
440 	if (hwconfig("can"))
441 		conflict_flag++;
442 	if (hwconfig("sai"))
443 		conflict_flag++;
444 	if (conflict_flag > 1) {
445 		printf("WARNING: pin conflict !\n");
446 		return 0;
447 	}
448 
449 	if (hwconfig("can"))
450 		config_board_mux(MUX_TYPE_CAN);
451 	else if (hwconfig("rgmii"))
452 		config_board_mux(MUX_TYPE_RGMII);
453 	else if (hwconfig("sai"))
454 		config_board_mux(MUX_TYPE_SAI);
455 
456 	if (hwconfig("iic2"))
457 		config_board_mux(MUX_TYPE_IIC2);
458 	else if (hwconfig("sdhc"))
459 		config_board_mux(MUX_TYPE_SDHC);
460 
461 #ifdef CONFIG_FSL_DEVICE_DISABLE
462 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
463 #endif
464 #ifdef CONFIG_FSL_CAAM
465 	return sec_init();
466 #endif
467 	return 0;
468 }
469 
470 struct liodn_id_table sec_liodn_tbl[] = {
471 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
472 	SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
473 	SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
474 	SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
475 	SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
476 	SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
477 	SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
478 	SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
479 	SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
480 	SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
481 	SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
482 	SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
483 	SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
484 	SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
485 	SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
486 	SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
487 };
488 
489 struct smmu_stream_id dev_stream_id[] = {
490 	{ 0x100, 0x01, "ETSEC MAC1" },
491 	{ 0x104, 0x02, "ETSEC MAC2" },
492 	{ 0x108, 0x03, "ETSEC MAC3" },
493 	{ 0x10c, 0x04, "PEX1" },
494 	{ 0x110, 0x05, "PEX2" },
495 	{ 0x114, 0x06, "qDMA" },
496 	{ 0x118, 0x07, "SATA" },
497 	{ 0x11c, 0x08, "USB3" },
498 	{ 0x120, 0x09, "QE" },
499 	{ 0x124, 0x0a, "eSDHC" },
500 	{ 0x128, 0x0b, "eMA" },
501 	{ 0x14c, 0x0c, "2D-ACE" },
502 	{ 0x150, 0x0d, "USB2" },
503 	{ 0x18c, 0x0e, "DEBUG" },
504 };
505 
506 int board_init(void)
507 {
508 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
509 	unsigned int major;
510 
511 	major = get_soc_major_rev();
512 	if (major == SOC_MAJOR_VER_1_0) {
513 		/* Set CCI-400 control override register to
514 		 * enable barrier transaction */
515 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
516 	}
517 
518 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
519 
520 #ifndef CONFIG_SYS_FSL_NO_SERDES
521 	fsl_serdes_init();
522 	config_serdes_mux();
523 #endif
524 
525 	ls1021x_config_caam_stream_id(sec_liodn_tbl,
526 				      ARRAY_SIZE(sec_liodn_tbl));
527 	ls102xa_config_smmu_stream_id(dev_stream_id,
528 				      ARRAY_SIZE(dev_stream_id));
529 
530 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
531 	enable_layerscape_ns_access();
532 #endif
533 
534 #ifdef CONFIG_U_QE
535 	u_qe_init();
536 #endif
537 
538 	return 0;
539 }
540 
541 #if defined(CONFIG_DEEP_SLEEP)
542 void board_sleep_prepare(void)
543 {
544 	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
545 	unsigned int major;
546 
547 	major = get_soc_major_rev();
548 	if (major == SOC_MAJOR_VER_1_0) {
549 		/* Set CCI-400 control override register to
550 		 * enable barrier transaction */
551 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
552 	}
553 
554 
555 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
556 	enable_layerscape_ns_access();
557 #endif
558 }
559 #endif
560 
561 int ft_board_setup(void *blob, bd_t *bd)
562 {
563 	ft_cpu_setup(blob, bd);
564 
565 #ifdef CONFIG_PCI
566 	ft_pci_setup(blob, bd);
567 #endif
568 
569 	return 0;
570 }
571 
572 u8 flash_read8(void *addr)
573 {
574 	return __raw_readb(addr + 1);
575 }
576 
577 void flash_write16(u16 val, void *addr)
578 {
579 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
580 
581 	__raw_writew(shftval, addr);
582 }
583 
584 u16 flash_read16(void *addr)
585 {
586 	u16 val = __raw_readw(addr);
587 
588 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
589 }
590