1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ls102xa_soc.h> 14 #include <asm/arch/ls102xa_devdis.h> 15 #include <asm/arch/ls102xa_sata.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <fsl_csu.h> 19 #include <fsl_esdhc.h> 20 #include <fsl_ifc.h> 21 #include <fsl_sec.h> 22 #include <spl.h> 23 #include <fsl_devdis.h> 24 #include <fsl_validate.h> 25 #include <fsl_ddr.h> 26 #include "../common/sleep.h" 27 #include "../common/qixis.h" 28 #include "ls1021aqds_qixis.h" 29 #ifdef CONFIG_U_QE 30 #include <fsl_qe.h> 31 #endif 32 33 #define PIN_MUX_SEL_CAN 0x03 34 #define PIN_MUX_SEL_IIC2 0xa0 35 #define PIN_MUX_SEL_RGMII 0x00 36 #define PIN_MUX_SEL_SAI 0x0c 37 #define PIN_MUX_SEL_SDHC 0x00 38 39 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 40 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 41 DECLARE_GLOBAL_DATA_PTR; 42 43 enum { 44 MUX_TYPE_CAN, 45 MUX_TYPE_IIC2, 46 MUX_TYPE_RGMII, 47 MUX_TYPE_SAI, 48 MUX_TYPE_SDHC, 49 MUX_TYPE_SD_PCI4, 50 MUX_TYPE_SD_PC_SA_SG_SG, 51 MUX_TYPE_SD_PC_SA_PC_SG, 52 MUX_TYPE_SD_PC_SG_SG, 53 }; 54 55 enum { 56 GE0_CLK125, 57 GE2_CLK125, 58 GE1_CLK125, 59 }; 60 61 int checkboard(void) 62 { 63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 64 char buf[64]; 65 #endif 66 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 67 u8 sw; 68 #endif 69 70 puts("Board: LS1021AQDS\n"); 71 72 #ifdef CONFIG_SD_BOOT 73 puts("SD\n"); 74 #elif CONFIG_QSPI_BOOT 75 puts("QSPI\n"); 76 #else 77 sw = QIXIS_READ(brdcfg[0]); 78 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 79 80 if (sw < 0x8) 81 printf("vBank: %d\n", sw); 82 else if (sw == 0x8) 83 puts("PromJet\n"); 84 else if (sw == 0x9) 85 puts("NAND\n"); 86 else if (sw == 0x15) 87 printf("IFCCard\n"); 88 else 89 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 90 #endif 91 92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 93 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 94 QIXIS_READ(id), QIXIS_READ(arch)); 95 96 printf("FPGA: v%d (%s), build %d\n", 97 (int)QIXIS_READ(scver), qixis_read_tag(buf), 98 (int)qixis_read_minor()); 99 #endif 100 101 return 0; 102 } 103 104 unsigned long get_board_sys_clk(void) 105 { 106 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 107 108 switch (sysclk_conf & 0x0f) { 109 case QIXIS_SYSCLK_64: 110 return 64000000; 111 case QIXIS_SYSCLK_83: 112 return 83333333; 113 case QIXIS_SYSCLK_100: 114 return 100000000; 115 case QIXIS_SYSCLK_125: 116 return 125000000; 117 case QIXIS_SYSCLK_133: 118 return 133333333; 119 case QIXIS_SYSCLK_150: 120 return 150000000; 121 case QIXIS_SYSCLK_160: 122 return 160000000; 123 case QIXIS_SYSCLK_166: 124 return 166666666; 125 } 126 return 66666666; 127 } 128 129 unsigned long get_board_ddr_clk(void) 130 { 131 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 132 133 switch ((ddrclk_conf & 0x30) >> 4) { 134 case QIXIS_DDRCLK_100: 135 return 100000000; 136 case QIXIS_DDRCLK_125: 137 return 125000000; 138 case QIXIS_DDRCLK_133: 139 return 133333333; 140 } 141 return 66666666; 142 } 143 144 int select_i2c_ch_pca9547(u8 ch) 145 { 146 int ret; 147 148 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 149 if (ret) { 150 puts("PCA: failed to select proper channel\n"); 151 return ret; 152 } 153 154 return 0; 155 } 156 157 int dram_init(void) 158 { 159 /* 160 * When resuming from deep sleep, the I2C channel may not be 161 * in the default channel. So, switch to the default channel 162 * before accessing DDR SPD. 163 */ 164 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 165 return fsl_initdram(); 166 } 167 168 #ifdef CONFIG_FSL_ESDHC 169 struct fsl_esdhc_cfg esdhc_cfg[1] = { 170 {CONFIG_SYS_FSL_ESDHC_ADDR}, 171 }; 172 173 int board_mmc_init(bd_t *bis) 174 { 175 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 176 177 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 178 } 179 #endif 180 181 int board_early_init_f(void) 182 { 183 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 184 185 #ifdef CONFIG_TSEC_ENET 186 /* clear BD & FR bits for BE BD's and frame data */ 187 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 188 #endif 189 190 #ifdef CONFIG_FSL_IFC 191 init_early_memctl_regs(); 192 #endif 193 194 arch_soc_init(); 195 196 #if defined(CONFIG_DEEP_SLEEP) 197 if (is_warm_boot()) 198 fsl_dp_disable_console(); 199 #endif 200 201 return 0; 202 } 203 204 #ifdef CONFIG_SPL_BUILD 205 void board_init_f(ulong dummy) 206 { 207 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 208 CONFIG_SYS_CCI400_OFFSET); 209 unsigned int major; 210 211 #ifdef CONFIG_NAND_BOOT 212 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 213 u32 porsr1, pinctl; 214 215 /* 216 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 217 * NAND boot because IFC signals > IFC_AD7 are not enabled. 218 * This workaround changes RCW source to make all signals enabled. 219 */ 220 porsr1 = in_be32(&gur->porsr1); 221 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 222 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 223 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 224 pinctl); 225 #endif 226 227 /* Clear the BSS */ 228 memset(__bss_start, 0, __bss_end - __bss_start); 229 230 #ifdef CONFIG_FSL_IFC 231 init_early_memctl_regs(); 232 #endif 233 234 get_clocks(); 235 236 #if defined(CONFIG_DEEP_SLEEP) 237 if (is_warm_boot()) 238 fsl_dp_disable_console(); 239 #endif 240 241 preloader_console_init(); 242 243 #ifdef CONFIG_SPL_I2C_SUPPORT 244 i2c_init_all(); 245 #endif 246 247 major = get_soc_major_rev(); 248 if (major == SOC_MAJOR_VER_1_0) 249 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 250 251 dram_init(); 252 253 /* Allow OCRAM access permission as R/W */ 254 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 255 enable_layerscape_ns_access(); 256 #endif 257 258 board_init_r(NULL, 0); 259 } 260 #endif 261 262 void config_etseccm_source(int etsec_gtx_125_mux) 263 { 264 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 265 266 switch (etsec_gtx_125_mux) { 267 case GE0_CLK125: 268 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); 269 debug("etseccm set to GE0_CLK125\n"); 270 break; 271 272 case GE2_CLK125: 273 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 274 debug("etseccm set to GE2_CLK125\n"); 275 break; 276 277 case GE1_CLK125: 278 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); 279 debug("etseccm set to GE1_CLK125\n"); 280 break; 281 282 default: 283 printf("Error! trying to set etseccm to invalid value\n"); 284 break; 285 } 286 } 287 288 int config_board_mux(int ctrl_type) 289 { 290 u8 reg12, reg14; 291 292 reg12 = QIXIS_READ(brdcfg[12]); 293 reg14 = QIXIS_READ(brdcfg[14]); 294 295 switch (ctrl_type) { 296 case MUX_TYPE_CAN: 297 config_etseccm_source(GE2_CLK125); 298 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 299 break; 300 case MUX_TYPE_IIC2: 301 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 302 break; 303 case MUX_TYPE_RGMII: 304 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 305 break; 306 case MUX_TYPE_SAI: 307 config_etseccm_source(GE2_CLK125); 308 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 309 break; 310 case MUX_TYPE_SDHC: 311 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 312 break; 313 case MUX_TYPE_SD_PCI4: 314 reg12 = 0x38; 315 break; 316 case MUX_TYPE_SD_PC_SA_SG_SG: 317 reg12 = 0x01; 318 break; 319 case MUX_TYPE_SD_PC_SA_PC_SG: 320 reg12 = 0x01; 321 break; 322 case MUX_TYPE_SD_PC_SG_SG: 323 reg12 = 0x21; 324 break; 325 default: 326 printf("Wrong mux interface type\n"); 327 return -1; 328 } 329 330 QIXIS_WRITE(brdcfg[12], reg12); 331 QIXIS_WRITE(brdcfg[14], reg14); 332 333 return 0; 334 } 335 336 int config_serdes_mux(void) 337 { 338 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 339 u32 cfg; 340 341 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 342 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 343 344 switch (cfg) { 345 case 0x0: 346 config_board_mux(MUX_TYPE_SD_PCI4); 347 break; 348 case 0x30: 349 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 350 break; 351 case 0x60: 352 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 353 break; 354 case 0x70: 355 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 356 break; 357 default: 358 printf("SRDS1 prtcl:0x%x\n", cfg); 359 break; 360 } 361 362 return 0; 363 } 364 365 #ifdef CONFIG_BOARD_LATE_INIT 366 int board_late_init(void) 367 { 368 #ifdef CONFIG_SCSI_AHCI_PLAT 369 ls1021a_sata_init(); 370 #endif 371 #ifdef CONFIG_CHAIN_OF_TRUST 372 fsl_setenv_chain_of_trust(); 373 #endif 374 375 return 0; 376 } 377 #endif 378 379 int misc_init_r(void) 380 { 381 int conflict_flag; 382 383 /* some signals can not enable simultaneous*/ 384 conflict_flag = 0; 385 if (hwconfig("sdhc")) 386 conflict_flag++; 387 if (hwconfig("iic2")) 388 conflict_flag++; 389 if (conflict_flag > 1) { 390 printf("WARNING: pin conflict !\n"); 391 return 0; 392 } 393 394 conflict_flag = 0; 395 if (hwconfig("rgmii")) 396 conflict_flag++; 397 if (hwconfig("can")) 398 conflict_flag++; 399 if (hwconfig("sai")) 400 conflict_flag++; 401 if (conflict_flag > 1) { 402 printf("WARNING: pin conflict !\n"); 403 return 0; 404 } 405 406 if (hwconfig("can")) 407 config_board_mux(MUX_TYPE_CAN); 408 else if (hwconfig("rgmii")) 409 config_board_mux(MUX_TYPE_RGMII); 410 else if (hwconfig("sai")) 411 config_board_mux(MUX_TYPE_SAI); 412 413 if (hwconfig("iic2")) 414 config_board_mux(MUX_TYPE_IIC2); 415 else if (hwconfig("sdhc")) 416 config_board_mux(MUX_TYPE_SDHC); 417 418 #ifdef CONFIG_FSL_DEVICE_DISABLE 419 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 420 #endif 421 #ifdef CONFIG_FSL_CAAM 422 return sec_init(); 423 #endif 424 return 0; 425 } 426 427 int board_init(void) 428 { 429 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 430 CONFIG_SYS_CCI400_OFFSET); 431 unsigned int major; 432 433 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 434 erratum_a010315(); 435 #endif 436 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 437 erratum_a009942_check_cpo(); 438 #endif 439 major = get_soc_major_rev(); 440 if (major == SOC_MAJOR_VER_1_0) { 441 /* Set CCI-400 control override register to 442 * enable barrier transaction */ 443 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 444 } 445 446 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 447 448 #ifndef CONFIG_SYS_FSL_NO_SERDES 449 fsl_serdes_init(); 450 config_serdes_mux(); 451 #endif 452 453 ls102xa_smmu_stream_id_init(); 454 455 #ifdef CONFIG_U_QE 456 u_qe_init(); 457 #endif 458 459 return 0; 460 } 461 462 #if defined(CONFIG_DEEP_SLEEP) 463 void board_sleep_prepare(void) 464 { 465 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 466 CONFIG_SYS_CCI400_OFFSET); 467 unsigned int major; 468 469 major = get_soc_major_rev(); 470 if (major == SOC_MAJOR_VER_1_0) { 471 /* Set CCI-400 control override register to 472 * enable barrier transaction */ 473 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 474 } 475 476 477 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 478 enable_layerscape_ns_access(); 479 #endif 480 } 481 #endif 482 483 int ft_board_setup(void *blob, bd_t *bd) 484 { 485 ft_cpu_setup(blob, bd); 486 487 #ifdef CONFIG_PCI 488 ft_pci_setup(blob, bd); 489 #endif 490 491 return 0; 492 } 493 494 u8 flash_read8(void *addr) 495 { 496 return __raw_readb(addr + 1); 497 } 498 499 void flash_write16(u16 val, void *addr) 500 { 501 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 502 503 __raw_writew(shftval, addr); 504 } 505 506 u16 flash_read16(void *addr) 507 { 508 u16 val = __raw_readw(addr); 509 510 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 511 } 512