1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <hwconfig.h>
15 #include <mmc.h>
16 #include <fsl_csu.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_ifc.h>
19 #include <fsl_sec.h>
20 #include <spl.h>
21 #include <fsl_devdis.h>
22 #include <fsl_validate.h>
23 #include <fsl_ddr.h>
24 #include "../common/sleep.h"
25 #include "../common/qixis.h"
26 #include "ls1021aqds_qixis.h"
27 #ifdef CONFIG_U_QE
28 #include <fsl_qe.h>
29 #endif
30 
31 #define PIN_MUX_SEL_CAN		0x03
32 #define PIN_MUX_SEL_IIC2	0xa0
33 #define PIN_MUX_SEL_RGMII	0x00
34 #define PIN_MUX_SEL_SAI		0x0c
35 #define PIN_MUX_SEL_SDHC	0x00
36 
37 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
38 #define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
39 enum {
40 	MUX_TYPE_CAN,
41 	MUX_TYPE_IIC2,
42 	MUX_TYPE_RGMII,
43 	MUX_TYPE_SAI,
44 	MUX_TYPE_SDHC,
45 	MUX_TYPE_SD_PCI4,
46 	MUX_TYPE_SD_PC_SA_SG_SG,
47 	MUX_TYPE_SD_PC_SA_PC_SG,
48 	MUX_TYPE_SD_PC_SG_SG,
49 };
50 
51 enum {
52 	GE0_CLK125,
53 	GE2_CLK125,
54 	GE1_CLK125,
55 };
56 
57 int checkboard(void)
58 {
59 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
60 	char buf[64];
61 #endif
62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
63 	u8 sw;
64 #endif
65 
66 	puts("Board: LS1021AQDS\n");
67 
68 #ifdef CONFIG_SD_BOOT
69 	puts("SD\n");
70 #elif CONFIG_QSPI_BOOT
71 	puts("QSPI\n");
72 #else
73 	sw = QIXIS_READ(brdcfg[0]);
74 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
75 
76 	if (sw < 0x8)
77 		printf("vBank: %d\n", sw);
78 	else if (sw == 0x8)
79 		puts("PromJet\n");
80 	else if (sw == 0x9)
81 		puts("NAND\n");
82 	else if (sw == 0x15)
83 		printf("IFCCard\n");
84 	else
85 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
86 #endif
87 
88 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
89 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
90 	       QIXIS_READ(id), QIXIS_READ(arch));
91 
92 	printf("FPGA:  v%d (%s), build %d\n",
93 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
94 	       (int)qixis_read_minor());
95 #endif
96 
97 	return 0;
98 }
99 
100 unsigned long get_board_sys_clk(void)
101 {
102 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
103 
104 	switch (sysclk_conf & 0x0f) {
105 	case QIXIS_SYSCLK_64:
106 		return 64000000;
107 	case QIXIS_SYSCLK_83:
108 		return 83333333;
109 	case QIXIS_SYSCLK_100:
110 		return 100000000;
111 	case QIXIS_SYSCLK_125:
112 		return 125000000;
113 	case QIXIS_SYSCLK_133:
114 		return 133333333;
115 	case QIXIS_SYSCLK_150:
116 		return 150000000;
117 	case QIXIS_SYSCLK_160:
118 		return 160000000;
119 	case QIXIS_SYSCLK_166:
120 		return 166666666;
121 	}
122 	return 66666666;
123 }
124 
125 unsigned long get_board_ddr_clk(void)
126 {
127 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
128 
129 	switch ((ddrclk_conf & 0x30) >> 4) {
130 	case QIXIS_DDRCLK_100:
131 		return 100000000;
132 	case QIXIS_DDRCLK_125:
133 		return 125000000;
134 	case QIXIS_DDRCLK_133:
135 		return 133333333;
136 	}
137 	return 66666666;
138 }
139 
140 int select_i2c_ch_pca9547(u8 ch)
141 {
142 	int ret;
143 
144 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
145 	if (ret) {
146 		puts("PCA: failed to select proper channel\n");
147 		return ret;
148 	}
149 
150 	return 0;
151 }
152 
153 int dram_init(void)
154 {
155 	/*
156 	 * When resuming from deep sleep, the I2C channel may not be
157 	 * in the default channel. So, switch to the default channel
158 	 * before accessing DDR SPD.
159 	 */
160 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 	return fsl_initdram();
162 }
163 
164 #ifdef CONFIG_FSL_ESDHC
165 struct fsl_esdhc_cfg esdhc_cfg[1] = {
166 	{CONFIG_SYS_FSL_ESDHC_ADDR},
167 };
168 
169 int board_mmc_init(bd_t *bis)
170 {
171 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
172 
173 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
174 }
175 #endif
176 
177 int board_early_init_f(void)
178 {
179 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
180 
181 #ifdef CONFIG_TSEC_ENET
182 	/* clear BD & FR bits for BE BD's and frame data */
183 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
184 #endif
185 
186 #ifdef CONFIG_FSL_IFC
187 	init_early_memctl_regs();
188 #endif
189 
190 	arch_soc_init();
191 
192 #if defined(CONFIG_DEEP_SLEEP)
193 	if (is_warm_boot())
194 		fsl_dp_disable_console();
195 #endif
196 
197 	return 0;
198 }
199 
200 #ifdef CONFIG_SPL_BUILD
201 void board_init_f(ulong dummy)
202 {
203 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
204 					CONFIG_SYS_CCI400_OFFSET);
205 	unsigned int major;
206 
207 #ifdef CONFIG_NAND_BOOT
208 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
209 	u32 porsr1, pinctl;
210 
211 	/*
212 	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
213 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
214 	 * This workaround changes RCW source to make all signals enabled.
215 	 */
216 	porsr1 = in_be32(&gur->porsr1);
217 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
218 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
219 	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
220 		 pinctl);
221 #endif
222 
223 	/* Clear the BSS */
224 	memset(__bss_start, 0, __bss_end - __bss_start);
225 
226 #ifdef CONFIG_FSL_IFC
227 	init_early_memctl_regs();
228 #endif
229 
230 	get_clocks();
231 
232 #if defined(CONFIG_DEEP_SLEEP)
233 	if (is_warm_boot())
234 		fsl_dp_disable_console();
235 #endif
236 
237 	preloader_console_init();
238 
239 #ifdef CONFIG_SPL_I2C_SUPPORT
240 	i2c_init_all();
241 #endif
242 
243 	major = get_soc_major_rev();
244 	if (major == SOC_MAJOR_VER_1_0)
245 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
246 
247 	timer_init();
248 	dram_init();
249 
250 	/* Allow OCRAM access permission as R/W */
251 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
252 	enable_layerscape_ns_access();
253 #endif
254 
255 	board_init_r(NULL, 0);
256 }
257 #endif
258 
259 void config_etseccm_source(int etsec_gtx_125_mux)
260 {
261 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
262 
263 	switch (etsec_gtx_125_mux) {
264 	case GE0_CLK125:
265 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
266 		debug("etseccm set to GE0_CLK125\n");
267 		break;
268 
269 	case GE2_CLK125:
270 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
271 		debug("etseccm set to GE2_CLK125\n");
272 		break;
273 
274 	case GE1_CLK125:
275 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
276 		debug("etseccm set to GE1_CLK125\n");
277 		break;
278 
279 	default:
280 		printf("Error! trying to set etseccm to invalid value\n");
281 		break;
282 	}
283 }
284 
285 int config_board_mux(int ctrl_type)
286 {
287 	u8 reg12, reg14;
288 
289 	reg12 = QIXIS_READ(brdcfg[12]);
290 	reg14 = QIXIS_READ(brdcfg[14]);
291 
292 	switch (ctrl_type) {
293 	case MUX_TYPE_CAN:
294 		config_etseccm_source(GE2_CLK125);
295 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
296 		break;
297 	case MUX_TYPE_IIC2:
298 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
299 		break;
300 	case MUX_TYPE_RGMII:
301 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
302 		break;
303 	case MUX_TYPE_SAI:
304 		config_etseccm_source(GE2_CLK125);
305 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
306 		break;
307 	case MUX_TYPE_SDHC:
308 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
309 		break;
310 	case MUX_TYPE_SD_PCI4:
311 		reg12 = 0x38;
312 		break;
313 	case MUX_TYPE_SD_PC_SA_SG_SG:
314 		reg12 = 0x01;
315 		break;
316 	case MUX_TYPE_SD_PC_SA_PC_SG:
317 		reg12 = 0x01;
318 		break;
319 	case MUX_TYPE_SD_PC_SG_SG:
320 		reg12 = 0x21;
321 		break;
322 	default:
323 		printf("Wrong mux interface type\n");
324 		return -1;
325 	}
326 
327 	QIXIS_WRITE(brdcfg[12], reg12);
328 	QIXIS_WRITE(brdcfg[14], reg14);
329 
330 	return 0;
331 }
332 
333 int config_serdes_mux(void)
334 {
335 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
336 	u32 cfg;
337 
338 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
339 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
340 
341 	switch (cfg) {
342 	case 0x0:
343 		config_board_mux(MUX_TYPE_SD_PCI4);
344 		break;
345 	case 0x30:
346 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
347 		break;
348 	case 0x60:
349 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
350 		break;
351 	case 0x70:
352 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
353 		break;
354 	default:
355 		printf("SRDS1 prtcl:0x%x\n", cfg);
356 		break;
357 	}
358 
359 	return 0;
360 }
361 
362 #ifdef CONFIG_BOARD_LATE_INIT
363 int board_late_init(void)
364 {
365 #ifdef CONFIG_CHAIN_OF_TRUST
366 	fsl_setenv_chain_of_trust();
367 #endif
368 
369 	return 0;
370 }
371 #endif
372 
373 int misc_init_r(void)
374 {
375 	int conflict_flag;
376 
377 	/* some signals can not enable simultaneous*/
378 	conflict_flag = 0;
379 	if (hwconfig("sdhc"))
380 		conflict_flag++;
381 	if (hwconfig("iic2"))
382 		conflict_flag++;
383 	if (conflict_flag > 1) {
384 		printf("WARNING: pin conflict !\n");
385 		return 0;
386 	}
387 
388 	conflict_flag = 0;
389 	if (hwconfig("rgmii"))
390 		conflict_flag++;
391 	if (hwconfig("can"))
392 		conflict_flag++;
393 	if (hwconfig("sai"))
394 		conflict_flag++;
395 	if (conflict_flag > 1) {
396 		printf("WARNING: pin conflict !\n");
397 		return 0;
398 	}
399 
400 	if (hwconfig("can"))
401 		config_board_mux(MUX_TYPE_CAN);
402 	else if (hwconfig("rgmii"))
403 		config_board_mux(MUX_TYPE_RGMII);
404 	else if (hwconfig("sai"))
405 		config_board_mux(MUX_TYPE_SAI);
406 
407 	if (hwconfig("iic2"))
408 		config_board_mux(MUX_TYPE_IIC2);
409 	else if (hwconfig("sdhc"))
410 		config_board_mux(MUX_TYPE_SDHC);
411 
412 #ifdef CONFIG_FSL_DEVICE_DISABLE
413 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
414 #endif
415 #ifdef CONFIG_FSL_CAAM
416 	return sec_init();
417 #endif
418 	return 0;
419 }
420 
421 int board_init(void)
422 {
423 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
424 					CONFIG_SYS_CCI400_OFFSET);
425 	unsigned int major;
426 
427 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
428 	erratum_a010315();
429 #endif
430 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
431 	erratum_a009942_check_cpo();
432 #endif
433 	major = get_soc_major_rev();
434 	if (major == SOC_MAJOR_VER_1_0) {
435 		/* Set CCI-400 control override register to
436 		 * enable barrier transaction */
437 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
438 	}
439 
440 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
441 
442 #ifndef CONFIG_SYS_FSL_NO_SERDES
443 	fsl_serdes_init();
444 	config_serdes_mux();
445 #endif
446 
447 	ls102xa_smmu_stream_id_init();
448 
449 #ifdef CONFIG_U_QE
450 	u_qe_init();
451 #endif
452 
453 	return 0;
454 }
455 
456 #if defined(CONFIG_DEEP_SLEEP)
457 void board_sleep_prepare(void)
458 {
459 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
460 						CONFIG_SYS_CCI400_OFFSET);
461 	unsigned int major;
462 
463 	major = get_soc_major_rev();
464 	if (major == SOC_MAJOR_VER_1_0) {
465 		/* Set CCI-400 control override register to
466 		 * enable barrier transaction */
467 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
468 	}
469 
470 
471 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
472 	enable_layerscape_ns_access();
473 #endif
474 }
475 #endif
476 
477 int ft_board_setup(void *blob, bd_t *bd)
478 {
479 	ft_cpu_setup(blob, bd);
480 
481 #ifdef CONFIG_PCI
482 	ft_pci_setup(blob, bd);
483 #endif
484 
485 	return 0;
486 }
487 
488 u8 flash_read8(void *addr)
489 {
490 	return __raw_readb(addr + 1);
491 }
492 
493 void flash_write16(u16 val, void *addr)
494 {
495 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
496 
497 	__raw_writew(shftval, addr);
498 }
499 
500 u16 flash_read16(void *addr)
501 {
502 	u16 val = __raw_readw(addr);
503 
504 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
505 }
506