1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/pcie_layerscape.h> 14 #include <hwconfig.h> 15 #include <mmc.h> 16 #include <fsl_esdhc.h> 17 #include <fsl_ifc.h> 18 #include <fsl_sec.h> 19 #include <spl.h> 20 21 #include "../common/qixis.h" 22 #include "ls1021aqds_qixis.h" 23 #ifdef CONFIG_U_QE 24 #include "../../../drivers/qe/qe.h" 25 #endif 26 27 #define PIN_MUX_SEL_CAN 0x03 28 #define PIN_MUX_SEL_IIC2 0xa0 29 #define PIN_MUX_SEL_RGMII 0x00 30 #define PIN_MUX_SEL_SAI 0x0c 31 #define PIN_MUX_SEL_SDHC 0x00 32 33 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 34 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 35 DECLARE_GLOBAL_DATA_PTR; 36 37 enum { 38 MUX_TYPE_CAN, 39 MUX_TYPE_IIC2, 40 MUX_TYPE_RGMII, 41 MUX_TYPE_SAI, 42 MUX_TYPE_SDHC, 43 MUX_TYPE_SD_PCI4, 44 MUX_TYPE_SD_PC_SA_SG_SG, 45 MUX_TYPE_SD_PC_SA_PC_SG, 46 MUX_TYPE_SD_PC_SG_SG, 47 }; 48 49 int checkboard(void) 50 { 51 #ifndef CONFIG_QSPI_BOOT 52 char buf[64]; 53 #endif 54 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 55 u8 sw; 56 #endif 57 58 puts("Board: LS1021AQDS\n"); 59 60 #ifdef CONFIG_SD_BOOT 61 puts("SD\n"); 62 #elif CONFIG_QSPI_BOOT 63 puts("QSPI\n"); 64 #else 65 sw = QIXIS_READ(brdcfg[0]); 66 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 67 68 if (sw < 0x8) 69 printf("vBank: %d\n", sw); 70 else if (sw == 0x8) 71 puts("PromJet\n"); 72 else if (sw == 0x9) 73 puts("NAND\n"); 74 else if (sw == 0x15) 75 printf("IFCCard\n"); 76 else 77 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 78 #endif 79 80 #ifndef CONFIG_QSPI_BOOT 81 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 82 QIXIS_READ(id), QIXIS_READ(arch)); 83 84 printf("FPGA: v%d (%s), build %d\n", 85 (int)QIXIS_READ(scver), qixis_read_tag(buf), 86 (int)qixis_read_minor()); 87 #endif 88 89 return 0; 90 } 91 92 unsigned long get_board_sys_clk(void) 93 { 94 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 95 96 switch (sysclk_conf & 0x0f) { 97 case QIXIS_SYSCLK_64: 98 return 64000000; 99 case QIXIS_SYSCLK_83: 100 return 83333333; 101 case QIXIS_SYSCLK_100: 102 return 100000000; 103 case QIXIS_SYSCLK_125: 104 return 125000000; 105 case QIXIS_SYSCLK_133: 106 return 133333333; 107 case QIXIS_SYSCLK_150: 108 return 150000000; 109 case QIXIS_SYSCLK_160: 110 return 160000000; 111 case QIXIS_SYSCLK_166: 112 return 166666666; 113 } 114 return 66666666; 115 } 116 117 unsigned long get_board_ddr_clk(void) 118 { 119 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 120 121 switch ((ddrclk_conf & 0x30) >> 4) { 122 case QIXIS_DDRCLK_100: 123 return 100000000; 124 case QIXIS_DDRCLK_125: 125 return 125000000; 126 case QIXIS_DDRCLK_133: 127 return 133333333; 128 } 129 return 66666666; 130 } 131 132 int select_i2c_ch_pca9547(u8 ch) 133 { 134 int ret; 135 136 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 137 if (ret) { 138 puts("PCA: failed to select proper channel\n"); 139 return ret; 140 } 141 142 return 0; 143 } 144 145 int dram_init(void) 146 { 147 /* 148 * When resuming from deep sleep, the I2C channel may not be 149 * in the default channel. So, switch to the default channel 150 * before accessing DDR SPD. 151 */ 152 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 153 gd->ram_size = initdram(0); 154 155 return 0; 156 } 157 158 #ifdef CONFIG_FSL_ESDHC 159 struct fsl_esdhc_cfg esdhc_cfg[1] = { 160 {CONFIG_SYS_FSL_ESDHC_ADDR}, 161 }; 162 163 int board_mmc_init(bd_t *bis) 164 { 165 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 166 167 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 168 } 169 #endif 170 171 int board_early_init_f(void) 172 { 173 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 174 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 175 176 #ifdef CONFIG_TSEC_ENET 177 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 178 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 179 #endif 180 181 #ifdef CONFIG_FSL_IFC 182 init_early_memctl_regs(); 183 #endif 184 185 #ifdef CONFIG_FSL_QSPI 186 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 187 #endif 188 189 /* Workaround for the issue that DDR could not respond to 190 * barrier transaction which is generated by executing DSB/ISB 191 * instruction. Set CCI-400 control override register to 192 * terminate the barrier transaction. After DDR is initialized, 193 * allow barrier transaction to DDR again */ 194 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 195 196 return 0; 197 } 198 199 #ifdef CONFIG_SPL_BUILD 200 void board_init_f(ulong dummy) 201 { 202 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 203 204 #ifdef CONFIG_NAND_BOOT 205 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 206 u32 porsr1, pinctl; 207 208 /* 209 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 210 * NAND boot because IFC signals > IFC_AD7 are not enabled. 211 * This workaround changes RCW source to make all signals enabled. 212 */ 213 porsr1 = in_be32(&gur->porsr1); 214 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 215 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 216 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 217 pinctl); 218 #endif 219 220 /* Set global data pointer */ 221 gd = &gdata; 222 223 /* Clear the BSS */ 224 memset(__bss_start, 0, __bss_end - __bss_start); 225 226 #ifdef CONFIG_FSL_IFC 227 init_early_memctl_regs(); 228 #endif 229 230 get_clocks(); 231 232 preloader_console_init(); 233 234 #ifdef CONFIG_SPL_I2C_SUPPORT 235 i2c_init_all(); 236 #endif 237 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 238 239 dram_init(); 240 241 board_init_r(NULL, 0); 242 } 243 #endif 244 245 int config_board_mux(int ctrl_type) 246 { 247 u8 reg12, reg14; 248 249 reg12 = QIXIS_READ(brdcfg[12]); 250 reg14 = QIXIS_READ(brdcfg[14]); 251 252 switch (ctrl_type) { 253 case MUX_TYPE_CAN: 254 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 255 break; 256 case MUX_TYPE_IIC2: 257 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 258 break; 259 case MUX_TYPE_RGMII: 260 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 261 break; 262 case MUX_TYPE_SAI: 263 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 264 break; 265 case MUX_TYPE_SDHC: 266 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 267 break; 268 case MUX_TYPE_SD_PCI4: 269 reg12 = 0x38; 270 break; 271 case MUX_TYPE_SD_PC_SA_SG_SG: 272 reg12 = 0x01; 273 break; 274 case MUX_TYPE_SD_PC_SA_PC_SG: 275 reg12 = 0x01; 276 break; 277 case MUX_TYPE_SD_PC_SG_SG: 278 reg12 = 0x21; 279 break; 280 default: 281 printf("Wrong mux interface type\n"); 282 return -1; 283 } 284 285 QIXIS_WRITE(brdcfg[12], reg12); 286 QIXIS_WRITE(brdcfg[14], reg14); 287 288 return 0; 289 } 290 291 int config_serdes_mux(void) 292 { 293 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 294 u32 cfg; 295 296 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 297 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 298 299 switch (cfg) { 300 case 0x0: 301 config_board_mux(MUX_TYPE_SD_PCI4); 302 break; 303 case 0x30: 304 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 305 break; 306 case 0x60: 307 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 308 break; 309 case 0x70: 310 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 311 break; 312 default: 313 printf("SRDS1 prtcl:0x%x\n", cfg); 314 break; 315 } 316 317 return 0; 318 } 319 320 int misc_init_r(void) 321 { 322 int conflict_flag; 323 324 /* some signals can not enable simultaneous*/ 325 conflict_flag = 0; 326 if (hwconfig("sdhc")) 327 conflict_flag++; 328 if (hwconfig("iic2")) 329 conflict_flag++; 330 if (conflict_flag > 1) { 331 printf("WARNING: pin conflict !\n"); 332 return 0; 333 } 334 335 conflict_flag = 0; 336 if (hwconfig("rgmii")) 337 conflict_flag++; 338 if (hwconfig("can")) 339 conflict_flag++; 340 if (hwconfig("sai")) 341 conflict_flag++; 342 if (conflict_flag > 1) { 343 printf("WARNING: pin conflict !\n"); 344 return 0; 345 } 346 347 if (hwconfig("can")) 348 config_board_mux(MUX_TYPE_CAN); 349 else if (hwconfig("rgmii")) 350 config_board_mux(MUX_TYPE_RGMII); 351 else if (hwconfig("sai")) 352 config_board_mux(MUX_TYPE_SAI); 353 354 if (hwconfig("iic2")) 355 config_board_mux(MUX_TYPE_IIC2); 356 else if (hwconfig("sdhc")) 357 config_board_mux(MUX_TYPE_SDHC); 358 359 #ifdef CONFIG_FSL_CAAM 360 return sec_init(); 361 #endif 362 return 0; 363 } 364 365 int board_init(void) 366 { 367 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 368 369 /* Set CCI-400 control override register to 370 * enable barrier transaction */ 371 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 372 /* 373 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register 374 * All transactions are treated as non-shareable 375 */ 376 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 377 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 378 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 379 380 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 381 382 #ifndef CONFIG_SYS_FSL_NO_SERDES 383 fsl_serdes_init(); 384 config_serdes_mux(); 385 #endif 386 387 #ifdef CONFIG_U_QE 388 u_qe_init(); 389 #endif 390 391 return 0; 392 } 393 394 int ft_board_setup(void *blob, bd_t *bd) 395 { 396 ft_cpu_setup(blob, bd); 397 398 #ifdef CONFIG_PCIE_LAYERSCAPE 399 ft_pcie_setup(blob, bd); 400 #endif 401 402 return 0; 403 } 404 405 u8 flash_read8(void *addr) 406 { 407 return __raw_readb(addr + 1); 408 } 409 410 void flash_write16(u16 val, void *addr) 411 { 412 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 413 414 __raw_writew(shftval, addr); 415 } 416 417 u16 flash_read16(void *addr) 418 { 419 u16 val = __raw_readw(addr); 420 421 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 422 } 423