1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <asm/io.h> 9 #include <asm/arch/immap_ls102xa.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/ls102xa_soc.h> 13 #include <asm/arch/ls102xa_devdis.h> 14 #include <asm/arch/ls102xa_sata.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <fsl_csu.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_sec.h> 21 #include <spl.h> 22 #include <fsl_devdis.h> 23 #include <fsl_validate.h> 24 #include <fsl_ddr.h> 25 #include "../common/sleep.h" 26 #include "../common/qixis.h" 27 #include "ls1021aqds_qixis.h" 28 #ifdef CONFIG_U_QE 29 #include <fsl_qe.h> 30 #endif 31 32 #define PIN_MUX_SEL_CAN 0x03 33 #define PIN_MUX_SEL_IIC2 0xa0 34 #define PIN_MUX_SEL_RGMII 0x00 35 #define PIN_MUX_SEL_SAI 0x0c 36 #define PIN_MUX_SEL_SDHC 0x00 37 38 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 39 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 40 enum { 41 MUX_TYPE_CAN, 42 MUX_TYPE_IIC2, 43 MUX_TYPE_RGMII, 44 MUX_TYPE_SAI, 45 MUX_TYPE_SDHC, 46 MUX_TYPE_SD_PCI4, 47 MUX_TYPE_SD_PC_SA_SG_SG, 48 MUX_TYPE_SD_PC_SA_PC_SG, 49 MUX_TYPE_SD_PC_SG_SG, 50 }; 51 52 enum { 53 GE0_CLK125, 54 GE2_CLK125, 55 GE1_CLK125, 56 }; 57 58 int checkboard(void) 59 { 60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 61 char buf[64]; 62 #endif 63 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 64 u8 sw; 65 #endif 66 67 puts("Board: LS1021AQDS\n"); 68 69 #ifdef CONFIG_SD_BOOT 70 puts("SD\n"); 71 #elif CONFIG_QSPI_BOOT 72 puts("QSPI\n"); 73 #else 74 sw = QIXIS_READ(brdcfg[0]); 75 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 76 77 if (sw < 0x8) 78 printf("vBank: %d\n", sw); 79 else if (sw == 0x8) 80 puts("PromJet\n"); 81 else if (sw == 0x9) 82 puts("NAND\n"); 83 else if (sw == 0x15) 84 printf("IFCCard\n"); 85 else 86 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 87 #endif 88 89 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 90 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 91 QIXIS_READ(id), QIXIS_READ(arch)); 92 93 printf("FPGA: v%d (%s), build %d\n", 94 (int)QIXIS_READ(scver), qixis_read_tag(buf), 95 (int)qixis_read_minor()); 96 #endif 97 98 return 0; 99 } 100 101 unsigned long get_board_sys_clk(void) 102 { 103 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 104 105 switch (sysclk_conf & 0x0f) { 106 case QIXIS_SYSCLK_64: 107 return 64000000; 108 case QIXIS_SYSCLK_83: 109 return 83333333; 110 case QIXIS_SYSCLK_100: 111 return 100000000; 112 case QIXIS_SYSCLK_125: 113 return 125000000; 114 case QIXIS_SYSCLK_133: 115 return 133333333; 116 case QIXIS_SYSCLK_150: 117 return 150000000; 118 case QIXIS_SYSCLK_160: 119 return 160000000; 120 case QIXIS_SYSCLK_166: 121 return 166666666; 122 } 123 return 66666666; 124 } 125 126 unsigned long get_board_ddr_clk(void) 127 { 128 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 129 130 switch ((ddrclk_conf & 0x30) >> 4) { 131 case QIXIS_DDRCLK_100: 132 return 100000000; 133 case QIXIS_DDRCLK_125: 134 return 125000000; 135 case QIXIS_DDRCLK_133: 136 return 133333333; 137 } 138 return 66666666; 139 } 140 141 int select_i2c_ch_pca9547(u8 ch) 142 { 143 int ret; 144 145 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 146 if (ret) { 147 puts("PCA: failed to select proper channel\n"); 148 return ret; 149 } 150 151 return 0; 152 } 153 154 int dram_init(void) 155 { 156 /* 157 * When resuming from deep sleep, the I2C channel may not be 158 * in the default channel. So, switch to the default channel 159 * before accessing DDR SPD. 160 */ 161 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 162 return fsl_initdram(); 163 } 164 165 #ifdef CONFIG_FSL_ESDHC 166 struct fsl_esdhc_cfg esdhc_cfg[1] = { 167 {CONFIG_SYS_FSL_ESDHC_ADDR}, 168 }; 169 170 int board_mmc_init(bd_t *bis) 171 { 172 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 173 174 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 175 } 176 #endif 177 178 int board_early_init_f(void) 179 { 180 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 181 182 #ifdef CONFIG_TSEC_ENET 183 /* clear BD & FR bits for BE BD's and frame data */ 184 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 185 #endif 186 187 #ifdef CONFIG_FSL_IFC 188 init_early_memctl_regs(); 189 #endif 190 191 arch_soc_init(); 192 193 #if defined(CONFIG_DEEP_SLEEP) 194 if (is_warm_boot()) 195 fsl_dp_disable_console(); 196 #endif 197 198 return 0; 199 } 200 201 #ifdef CONFIG_SPL_BUILD 202 void board_init_f(ulong dummy) 203 { 204 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 205 CONFIG_SYS_CCI400_OFFSET); 206 unsigned int major; 207 208 #ifdef CONFIG_NAND_BOOT 209 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 210 u32 porsr1, pinctl; 211 212 /* 213 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 214 * NAND boot because IFC signals > IFC_AD7 are not enabled. 215 * This workaround changes RCW source to make all signals enabled. 216 */ 217 porsr1 = in_be32(&gur->porsr1); 218 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 219 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 220 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 221 pinctl); 222 #endif 223 224 /* Clear the BSS */ 225 memset(__bss_start, 0, __bss_end - __bss_start); 226 227 #ifdef CONFIG_FSL_IFC 228 init_early_memctl_regs(); 229 #endif 230 231 get_clocks(); 232 233 #if defined(CONFIG_DEEP_SLEEP) 234 if (is_warm_boot()) 235 fsl_dp_disable_console(); 236 #endif 237 238 preloader_console_init(); 239 240 #ifdef CONFIG_SPL_I2C_SUPPORT 241 i2c_init_all(); 242 #endif 243 244 major = get_soc_major_rev(); 245 if (major == SOC_MAJOR_VER_1_0) 246 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 247 248 dram_init(); 249 250 /* Allow OCRAM access permission as R/W */ 251 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 252 enable_layerscape_ns_access(); 253 #endif 254 255 board_init_r(NULL, 0); 256 } 257 #endif 258 259 void config_etseccm_source(int etsec_gtx_125_mux) 260 { 261 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 262 263 switch (etsec_gtx_125_mux) { 264 case GE0_CLK125: 265 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); 266 debug("etseccm set to GE0_CLK125\n"); 267 break; 268 269 case GE2_CLK125: 270 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 271 debug("etseccm set to GE2_CLK125\n"); 272 break; 273 274 case GE1_CLK125: 275 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); 276 debug("etseccm set to GE1_CLK125\n"); 277 break; 278 279 default: 280 printf("Error! trying to set etseccm to invalid value\n"); 281 break; 282 } 283 } 284 285 int config_board_mux(int ctrl_type) 286 { 287 u8 reg12, reg14; 288 289 reg12 = QIXIS_READ(brdcfg[12]); 290 reg14 = QIXIS_READ(brdcfg[14]); 291 292 switch (ctrl_type) { 293 case MUX_TYPE_CAN: 294 config_etseccm_source(GE2_CLK125); 295 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 296 break; 297 case MUX_TYPE_IIC2: 298 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 299 break; 300 case MUX_TYPE_RGMII: 301 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 302 break; 303 case MUX_TYPE_SAI: 304 config_etseccm_source(GE2_CLK125); 305 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 306 break; 307 case MUX_TYPE_SDHC: 308 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 309 break; 310 case MUX_TYPE_SD_PCI4: 311 reg12 = 0x38; 312 break; 313 case MUX_TYPE_SD_PC_SA_SG_SG: 314 reg12 = 0x01; 315 break; 316 case MUX_TYPE_SD_PC_SA_PC_SG: 317 reg12 = 0x01; 318 break; 319 case MUX_TYPE_SD_PC_SG_SG: 320 reg12 = 0x21; 321 break; 322 default: 323 printf("Wrong mux interface type\n"); 324 return -1; 325 } 326 327 QIXIS_WRITE(brdcfg[12], reg12); 328 QIXIS_WRITE(brdcfg[14], reg14); 329 330 return 0; 331 } 332 333 int config_serdes_mux(void) 334 { 335 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 336 u32 cfg; 337 338 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 339 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 340 341 switch (cfg) { 342 case 0x0: 343 config_board_mux(MUX_TYPE_SD_PCI4); 344 break; 345 case 0x30: 346 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 347 break; 348 case 0x60: 349 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 350 break; 351 case 0x70: 352 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 353 break; 354 default: 355 printf("SRDS1 prtcl:0x%x\n", cfg); 356 break; 357 } 358 359 return 0; 360 } 361 362 #ifdef CONFIG_BOARD_LATE_INIT 363 int board_late_init(void) 364 { 365 #ifdef CONFIG_SCSI_AHCI_PLAT 366 ls1021a_sata_init(); 367 #endif 368 #ifdef CONFIG_CHAIN_OF_TRUST 369 fsl_setenv_chain_of_trust(); 370 #endif 371 372 return 0; 373 } 374 #endif 375 376 int misc_init_r(void) 377 { 378 int conflict_flag; 379 380 /* some signals can not enable simultaneous*/ 381 conflict_flag = 0; 382 if (hwconfig("sdhc")) 383 conflict_flag++; 384 if (hwconfig("iic2")) 385 conflict_flag++; 386 if (conflict_flag > 1) { 387 printf("WARNING: pin conflict !\n"); 388 return 0; 389 } 390 391 conflict_flag = 0; 392 if (hwconfig("rgmii")) 393 conflict_flag++; 394 if (hwconfig("can")) 395 conflict_flag++; 396 if (hwconfig("sai")) 397 conflict_flag++; 398 if (conflict_flag > 1) { 399 printf("WARNING: pin conflict !\n"); 400 return 0; 401 } 402 403 if (hwconfig("can")) 404 config_board_mux(MUX_TYPE_CAN); 405 else if (hwconfig("rgmii")) 406 config_board_mux(MUX_TYPE_RGMII); 407 else if (hwconfig("sai")) 408 config_board_mux(MUX_TYPE_SAI); 409 410 if (hwconfig("iic2")) 411 config_board_mux(MUX_TYPE_IIC2); 412 else if (hwconfig("sdhc")) 413 config_board_mux(MUX_TYPE_SDHC); 414 415 #ifdef CONFIG_FSL_DEVICE_DISABLE 416 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 417 #endif 418 #ifdef CONFIG_FSL_CAAM 419 return sec_init(); 420 #endif 421 return 0; 422 } 423 424 int board_init(void) 425 { 426 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 427 CONFIG_SYS_CCI400_OFFSET); 428 unsigned int major; 429 430 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 431 erratum_a010315(); 432 #endif 433 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 434 erratum_a009942_check_cpo(); 435 #endif 436 major = get_soc_major_rev(); 437 if (major == SOC_MAJOR_VER_1_0) { 438 /* Set CCI-400 control override register to 439 * enable barrier transaction */ 440 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 441 } 442 443 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 444 445 #ifndef CONFIG_SYS_FSL_NO_SERDES 446 fsl_serdes_init(); 447 config_serdes_mux(); 448 #endif 449 450 ls102xa_smmu_stream_id_init(); 451 452 #ifdef CONFIG_U_QE 453 u_qe_init(); 454 #endif 455 456 return 0; 457 } 458 459 #if defined(CONFIG_DEEP_SLEEP) 460 void board_sleep_prepare(void) 461 { 462 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 463 CONFIG_SYS_CCI400_OFFSET); 464 unsigned int major; 465 466 major = get_soc_major_rev(); 467 if (major == SOC_MAJOR_VER_1_0) { 468 /* Set CCI-400 control override register to 469 * enable barrier transaction */ 470 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 471 } 472 473 474 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 475 enable_layerscape_ns_access(); 476 #endif 477 } 478 #endif 479 480 int ft_board_setup(void *blob, bd_t *bd) 481 { 482 ft_cpu_setup(blob, bd); 483 484 #ifdef CONFIG_PCI 485 ft_pci_setup(blob, bd); 486 #endif 487 488 return 0; 489 } 490 491 u8 flash_read8(void *addr) 492 { 493 return __raw_readb(addr + 1); 494 } 495 496 void flash_write16(u16 val, void *addr) 497 { 498 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 499 500 __raw_writew(shftval, addr); 501 } 502 503 u16 flash_read16(void *addr) 504 { 505 u16 val = __raw_readw(addr); 506 507 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 508 } 509