1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ns_access.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/ls102xa_stream_id.h> 15 #include <asm/arch/ls102xa_devdis.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_sec.h> 21 #include <spl.h> 22 #include <fsl_devdis.h> 23 24 #include "../common/sleep.h" 25 #include "../common/qixis.h" 26 #include "ls1021aqds_qixis.h" 27 #ifdef CONFIG_U_QE 28 #include "../../../drivers/qe/qe.h" 29 #endif 30 31 #define PIN_MUX_SEL_CAN 0x03 32 #define PIN_MUX_SEL_IIC2 0xa0 33 #define PIN_MUX_SEL_RGMII 0x00 34 #define PIN_MUX_SEL_SAI 0x0c 35 #define PIN_MUX_SEL_SDHC 0x00 36 37 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 38 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 39 DECLARE_GLOBAL_DATA_PTR; 40 41 enum { 42 MUX_TYPE_CAN, 43 MUX_TYPE_IIC2, 44 MUX_TYPE_RGMII, 45 MUX_TYPE_SAI, 46 MUX_TYPE_SDHC, 47 MUX_TYPE_SD_PCI4, 48 MUX_TYPE_SD_PC_SA_SG_SG, 49 MUX_TYPE_SD_PC_SA_PC_SG, 50 MUX_TYPE_SD_PC_SG_SG, 51 }; 52 53 enum { 54 GE0_CLK125, 55 GE2_CLK125, 56 GE1_CLK125, 57 }; 58 59 #ifdef CONFIG_LS102XA_NS_ACCESS 60 static struct csu_ns_dev ns_dev[] = { 61 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 62 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 63 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 64 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 65 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 66 { CSU_CSLX_GIC, CSU_ALL_RW }, 67 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 68 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 69 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 70 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 71 { CSU_CSLX_SATA, CSU_ALL_RW }, 72 { CSU_CSLX_USB3, CSU_ALL_RW }, 73 { CSU_CSLX_SERDES, CSU_ALL_RW }, 74 { CSU_CSLX_QDMA, CSU_ALL_RW }, 75 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 76 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 77 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 78 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 79 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 80 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 81 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 82 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 83 { CSU_CSLX_QSPI, CSU_ALL_RW }, 84 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 85 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 86 { CSU_CSLX_IFC, CSU_ALL_RW }, 87 { CSU_CSLX_I2C1, CSU_ALL_RW }, 88 { CSU_CSLX_USB2, CSU_ALL_RW }, 89 { CSU_CSLX_I2C3, CSU_ALL_RW }, 90 { CSU_CSLX_I2C2, CSU_ALL_RW }, 91 { CSU_CSLX_DUART2, CSU_ALL_RW }, 92 { CSU_CSLX_DUART1, CSU_ALL_RW }, 93 { CSU_CSLX_WDT2, CSU_ALL_RW }, 94 { CSU_CSLX_WDT1, CSU_ALL_RW }, 95 { CSU_CSLX_EDMA, CSU_ALL_RW }, 96 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 97 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 98 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 99 { CSU_CSLX_DDR, CSU_ALL_RW }, 100 { CSU_CSLX_QUICC, CSU_ALL_RW }, 101 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 102 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 103 { CSU_CSLX_SFP, CSU_ALL_RW }, 104 { CSU_CSLX_TMU, CSU_ALL_RW }, 105 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 106 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 107 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 108 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 109 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 110 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 111 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 112 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 113 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 114 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 115 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 116 { CSU_CSLX_CSU, CSU_ALL_RW }, 117 { CSU_CSLX_ASRC, CSU_ALL_RW }, 118 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 119 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 120 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 121 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 122 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 123 { CSU_CSLX_SAI2, CSU_ALL_RW }, 124 { CSU_CSLX_SAI1, CSU_ALL_RW }, 125 { CSU_CSLX_SAI4, CSU_ALL_RW }, 126 { CSU_CSLX_SAI3, CSU_ALL_RW }, 127 { CSU_CSLX_FTM2, CSU_ALL_RW }, 128 { CSU_CSLX_FTM1, CSU_ALL_RW }, 129 { CSU_CSLX_FTM4, CSU_ALL_RW }, 130 { CSU_CSLX_FTM3, CSU_ALL_RW }, 131 { CSU_CSLX_FTM6, CSU_ALL_RW }, 132 { CSU_CSLX_FTM5, CSU_ALL_RW }, 133 { CSU_CSLX_FTM8, CSU_ALL_RW }, 134 { CSU_CSLX_FTM7, CSU_ALL_RW }, 135 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 136 { CSU_CSLX_EPU, CSU_ALL_RW }, 137 { CSU_CSLX_GDI, CSU_ALL_RW }, 138 { CSU_CSLX_DDI, CSU_ALL_RW }, 139 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 140 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 141 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 142 }; 143 #endif 144 145 int checkboard(void) 146 { 147 #ifndef CONFIG_QSPI_BOOT 148 char buf[64]; 149 #endif 150 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 151 u8 sw; 152 #endif 153 154 puts("Board: LS1021AQDS\n"); 155 156 #ifdef CONFIG_SD_BOOT 157 puts("SD\n"); 158 #elif CONFIG_QSPI_BOOT 159 puts("QSPI\n"); 160 #else 161 sw = QIXIS_READ(brdcfg[0]); 162 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 163 164 if (sw < 0x8) 165 printf("vBank: %d\n", sw); 166 else if (sw == 0x8) 167 puts("PromJet\n"); 168 else if (sw == 0x9) 169 puts("NAND\n"); 170 else if (sw == 0x15) 171 printf("IFCCard\n"); 172 else 173 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 174 #endif 175 176 #ifndef CONFIG_QSPI_BOOT 177 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 178 QIXIS_READ(id), QIXIS_READ(arch)); 179 180 printf("FPGA: v%d (%s), build %d\n", 181 (int)QIXIS_READ(scver), qixis_read_tag(buf), 182 (int)qixis_read_minor()); 183 #endif 184 185 return 0; 186 } 187 188 unsigned long get_board_sys_clk(void) 189 { 190 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 191 192 switch (sysclk_conf & 0x0f) { 193 case QIXIS_SYSCLK_64: 194 return 64000000; 195 case QIXIS_SYSCLK_83: 196 return 83333333; 197 case QIXIS_SYSCLK_100: 198 return 100000000; 199 case QIXIS_SYSCLK_125: 200 return 125000000; 201 case QIXIS_SYSCLK_133: 202 return 133333333; 203 case QIXIS_SYSCLK_150: 204 return 150000000; 205 case QIXIS_SYSCLK_160: 206 return 160000000; 207 case QIXIS_SYSCLK_166: 208 return 166666666; 209 } 210 return 66666666; 211 } 212 213 unsigned long get_board_ddr_clk(void) 214 { 215 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 216 217 switch ((ddrclk_conf & 0x30) >> 4) { 218 case QIXIS_DDRCLK_100: 219 return 100000000; 220 case QIXIS_DDRCLK_125: 221 return 125000000; 222 case QIXIS_DDRCLK_133: 223 return 133333333; 224 } 225 return 66666666; 226 } 227 228 unsigned int get_soc_major_rev(void) 229 { 230 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 231 unsigned int svr, major; 232 233 svr = in_be32(&gur->svr); 234 major = SVR_MAJ(svr); 235 236 return major; 237 } 238 239 int select_i2c_ch_pca9547(u8 ch) 240 { 241 int ret; 242 243 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 244 if (ret) { 245 puts("PCA: failed to select proper channel\n"); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 int dram_init(void) 253 { 254 /* 255 * When resuming from deep sleep, the I2C channel may not be 256 * in the default channel. So, switch to the default channel 257 * before accessing DDR SPD. 258 */ 259 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 260 gd->ram_size = initdram(0); 261 262 return 0; 263 } 264 265 #ifdef CONFIG_FSL_ESDHC 266 struct fsl_esdhc_cfg esdhc_cfg[1] = { 267 {CONFIG_SYS_FSL_ESDHC_ADDR}, 268 }; 269 270 int board_mmc_init(bd_t *bis) 271 { 272 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 273 274 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 275 } 276 #endif 277 278 int board_early_init_f(void) 279 { 280 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 281 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 282 unsigned int major; 283 284 #ifdef CONFIG_TSEC_ENET 285 /* clear BD & FR bits for BE BD's and frame data */ 286 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 287 #endif 288 289 #ifdef CONFIG_FSL_IFC 290 init_early_memctl_regs(); 291 #endif 292 293 #ifdef CONFIG_FSL_QSPI 294 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 295 #endif 296 297 #ifdef CONFIG_FSL_DCU_FB 298 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 299 #endif 300 301 /* Configure Little endian for SAI, ASRC and SPDIF */ 302 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 303 304 /* 305 * Enable snoop requests and DVM message requests for 306 * Slave insterface S4 (A7 core cluster) 307 */ 308 out_le32(&cci->slave[4].snoop_ctrl, 309 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 310 311 major = get_soc_major_rev(); 312 if (major == SOC_MAJOR_VER_1_0) { 313 /* 314 * Set CCI-400 Slave interface S1, S2 Shareable Override 315 * Register All transactions are treated as non-shareable 316 */ 317 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 318 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 319 320 /* Workaround for the issue that DDR could not respond to 321 * barrier transaction which is generated by executing DSB/ISB 322 * instruction. Set CCI-400 control override register to 323 * terminate the barrier transaction. After DDR is initialized, 324 * allow barrier transaction to DDR again */ 325 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 326 } 327 328 #if defined(CONFIG_DEEP_SLEEP) 329 if (is_warm_boot()) 330 fsl_dp_disable_console(); 331 #endif 332 333 return 0; 334 } 335 336 #ifdef CONFIG_SPL_BUILD 337 void board_init_f(ulong dummy) 338 { 339 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 340 unsigned int major; 341 342 #ifdef CONFIG_NAND_BOOT 343 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 344 u32 porsr1, pinctl; 345 346 /* 347 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 348 * NAND boot because IFC signals > IFC_AD7 are not enabled. 349 * This workaround changes RCW source to make all signals enabled. 350 */ 351 porsr1 = in_be32(&gur->porsr1); 352 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 353 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 354 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 355 pinctl); 356 #endif 357 358 /* Clear the BSS */ 359 memset(__bss_start, 0, __bss_end - __bss_start); 360 361 #ifdef CONFIG_FSL_IFC 362 init_early_memctl_regs(); 363 #endif 364 365 get_clocks(); 366 367 #if defined(CONFIG_DEEP_SLEEP) 368 if (is_warm_boot()) 369 fsl_dp_disable_console(); 370 #endif 371 372 preloader_console_init(); 373 374 #ifdef CONFIG_SPL_I2C_SUPPORT 375 i2c_init_all(); 376 #endif 377 378 major = get_soc_major_rev(); 379 if (major == SOC_MAJOR_VER_1_0) 380 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 381 382 dram_init(); 383 384 /* Allow OCRAM access permission as R/W */ 385 #ifdef CONFIG_LS102XA_NS_ACCESS 386 enable_devices_ns_access(&ns_dev[4], 1); 387 enable_devices_ns_access(&ns_dev[7], 1); 388 #endif 389 390 board_init_r(NULL, 0); 391 } 392 #endif 393 394 void config_etseccm_source(int etsec_gtx_125_mux) 395 { 396 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 397 398 switch (etsec_gtx_125_mux) { 399 case GE0_CLK125: 400 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); 401 debug("etseccm set to GE0_CLK125\n"); 402 break; 403 404 case GE2_CLK125: 405 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 406 debug("etseccm set to GE2_CLK125\n"); 407 break; 408 409 case GE1_CLK125: 410 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); 411 debug("etseccm set to GE1_CLK125\n"); 412 break; 413 414 default: 415 printf("Error! trying to set etseccm to invalid value\n"); 416 break; 417 } 418 } 419 420 int config_board_mux(int ctrl_type) 421 { 422 u8 reg12, reg14; 423 424 reg12 = QIXIS_READ(brdcfg[12]); 425 reg14 = QIXIS_READ(brdcfg[14]); 426 427 switch (ctrl_type) { 428 case MUX_TYPE_CAN: 429 config_etseccm_source(GE2_CLK125); 430 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 431 break; 432 case MUX_TYPE_IIC2: 433 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 434 break; 435 case MUX_TYPE_RGMII: 436 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 437 break; 438 case MUX_TYPE_SAI: 439 config_etseccm_source(GE2_CLK125); 440 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 441 break; 442 case MUX_TYPE_SDHC: 443 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 444 break; 445 case MUX_TYPE_SD_PCI4: 446 reg12 = 0x38; 447 break; 448 case MUX_TYPE_SD_PC_SA_SG_SG: 449 reg12 = 0x01; 450 break; 451 case MUX_TYPE_SD_PC_SA_PC_SG: 452 reg12 = 0x01; 453 break; 454 case MUX_TYPE_SD_PC_SG_SG: 455 reg12 = 0x21; 456 break; 457 default: 458 printf("Wrong mux interface type\n"); 459 return -1; 460 } 461 462 QIXIS_WRITE(brdcfg[12], reg12); 463 QIXIS_WRITE(brdcfg[14], reg14); 464 465 return 0; 466 } 467 468 int config_serdes_mux(void) 469 { 470 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 471 u32 cfg; 472 473 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 474 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 475 476 switch (cfg) { 477 case 0x0: 478 config_board_mux(MUX_TYPE_SD_PCI4); 479 break; 480 case 0x30: 481 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 482 break; 483 case 0x60: 484 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 485 break; 486 case 0x70: 487 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 488 break; 489 default: 490 printf("SRDS1 prtcl:0x%x\n", cfg); 491 break; 492 } 493 494 return 0; 495 } 496 497 int misc_init_r(void) 498 { 499 int conflict_flag; 500 501 /* some signals can not enable simultaneous*/ 502 conflict_flag = 0; 503 if (hwconfig("sdhc")) 504 conflict_flag++; 505 if (hwconfig("iic2")) 506 conflict_flag++; 507 if (conflict_flag > 1) { 508 printf("WARNING: pin conflict !\n"); 509 return 0; 510 } 511 512 conflict_flag = 0; 513 if (hwconfig("rgmii")) 514 conflict_flag++; 515 if (hwconfig("can")) 516 conflict_flag++; 517 if (hwconfig("sai")) 518 conflict_flag++; 519 if (conflict_flag > 1) { 520 printf("WARNING: pin conflict !\n"); 521 return 0; 522 } 523 524 if (hwconfig("can")) 525 config_board_mux(MUX_TYPE_CAN); 526 else if (hwconfig("rgmii")) 527 config_board_mux(MUX_TYPE_RGMII); 528 else if (hwconfig("sai")) 529 config_board_mux(MUX_TYPE_SAI); 530 531 if (hwconfig("iic2")) 532 config_board_mux(MUX_TYPE_IIC2); 533 else if (hwconfig("sdhc")) 534 config_board_mux(MUX_TYPE_SDHC); 535 536 #ifdef CONFIG_FSL_DEVICE_DISABLE 537 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 538 #endif 539 #ifdef CONFIG_FSL_CAAM 540 return sec_init(); 541 #endif 542 return 0; 543 } 544 545 struct liodn_id_table sec_liodn_tbl[] = { 546 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 547 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 548 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 549 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 550 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 551 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 552 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 553 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 554 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 555 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 556 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 557 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 558 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 559 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 560 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 561 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 562 }; 563 564 struct smmu_stream_id dev_stream_id[] = { 565 { 0x100, 0x01, "ETSEC MAC1" }, 566 { 0x104, 0x02, "ETSEC MAC2" }, 567 { 0x108, 0x03, "ETSEC MAC3" }, 568 { 0x10c, 0x04, "PEX1" }, 569 { 0x110, 0x05, "PEX2" }, 570 { 0x114, 0x06, "qDMA" }, 571 { 0x118, 0x07, "SATA" }, 572 { 0x11c, 0x08, "USB3" }, 573 { 0x120, 0x09, "QE" }, 574 { 0x124, 0x0a, "eSDHC" }, 575 { 0x128, 0x0b, "eMA" }, 576 { 0x14c, 0x0c, "2D-ACE" }, 577 { 0x150, 0x0d, "USB2" }, 578 { 0x18c, 0x0e, "DEBUG" }, 579 }; 580 581 int board_init(void) 582 { 583 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 584 unsigned int major; 585 586 major = get_soc_major_rev(); 587 if (major == SOC_MAJOR_VER_1_0) { 588 /* Set CCI-400 control override register to 589 * enable barrier transaction */ 590 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 591 } 592 593 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 594 595 #ifndef CONFIG_SYS_FSL_NO_SERDES 596 fsl_serdes_init(); 597 config_serdes_mux(); 598 #endif 599 600 ls1021x_config_caam_stream_id(sec_liodn_tbl, 601 ARRAY_SIZE(sec_liodn_tbl)); 602 ls102xa_config_smmu_stream_id(dev_stream_id, 603 ARRAY_SIZE(dev_stream_id)); 604 605 #ifdef CONFIG_LS102XA_NS_ACCESS 606 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 607 #endif 608 609 #ifdef CONFIG_U_QE 610 u_qe_init(); 611 #endif 612 613 return 0; 614 } 615 616 #if defined(CONFIG_DEEP_SLEEP) 617 void board_sleep_prepare(void) 618 { 619 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 620 unsigned int major; 621 622 major = get_soc_major_rev(); 623 if (major == SOC_MAJOR_VER_1_0) { 624 /* Set CCI-400 control override register to 625 * enable barrier transaction */ 626 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 627 } 628 629 630 #ifdef CONFIG_LS102XA_NS_ACCESS 631 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 632 #endif 633 } 634 #endif 635 636 int ft_board_setup(void *blob, bd_t *bd) 637 { 638 ft_cpu_setup(blob, bd); 639 640 #ifdef CONFIG_PCI 641 ft_pci_setup(blob, bd); 642 #endif 643 644 return 0; 645 } 646 647 u8 flash_read8(void *addr) 648 { 649 return __raw_readb(addr + 1); 650 } 651 652 void flash_write16(u16 val, void *addr) 653 { 654 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 655 656 __raw_writew(shftval, addr); 657 } 658 659 u16 flash_read16(void *addr) 660 { 661 u16 val = __raw_readw(addr); 662 663 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 664 } 665