1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ns_access.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/ls102xa_stream_id.h> 15 #include <asm/pcie_layerscape.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_sec.h> 21 #include <spl.h> 22 23 #include "../common/qixis.h" 24 #include "ls1021aqds_qixis.h" 25 #ifdef CONFIG_U_QE 26 #include "../../../drivers/qe/qe.h" 27 #endif 28 29 #define PIN_MUX_SEL_CAN 0x03 30 #define PIN_MUX_SEL_IIC2 0xa0 31 #define PIN_MUX_SEL_RGMII 0x00 32 #define PIN_MUX_SEL_SAI 0x0c 33 #define PIN_MUX_SEL_SDHC 0x00 34 35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 36 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 37 DECLARE_GLOBAL_DATA_PTR; 38 39 enum { 40 MUX_TYPE_CAN, 41 MUX_TYPE_IIC2, 42 MUX_TYPE_RGMII, 43 MUX_TYPE_SAI, 44 MUX_TYPE_SDHC, 45 MUX_TYPE_SD_PCI4, 46 MUX_TYPE_SD_PC_SA_SG_SG, 47 MUX_TYPE_SD_PC_SA_PC_SG, 48 MUX_TYPE_SD_PC_SG_SG, 49 }; 50 51 int checkboard(void) 52 { 53 #ifndef CONFIG_QSPI_BOOT 54 char buf[64]; 55 #endif 56 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 57 u8 sw; 58 #endif 59 60 puts("Board: LS1021AQDS\n"); 61 62 #ifdef CONFIG_SD_BOOT 63 puts("SD\n"); 64 #elif CONFIG_QSPI_BOOT 65 puts("QSPI\n"); 66 #else 67 sw = QIXIS_READ(brdcfg[0]); 68 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 69 70 if (sw < 0x8) 71 printf("vBank: %d\n", sw); 72 else if (sw == 0x8) 73 puts("PromJet\n"); 74 else if (sw == 0x9) 75 puts("NAND\n"); 76 else if (sw == 0x15) 77 printf("IFCCard\n"); 78 else 79 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 80 #endif 81 82 #ifndef CONFIG_QSPI_BOOT 83 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 84 QIXIS_READ(id), QIXIS_READ(arch)); 85 86 printf("FPGA: v%d (%s), build %d\n", 87 (int)QIXIS_READ(scver), qixis_read_tag(buf), 88 (int)qixis_read_minor()); 89 #endif 90 91 return 0; 92 } 93 94 unsigned long get_board_sys_clk(void) 95 { 96 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 97 98 switch (sysclk_conf & 0x0f) { 99 case QIXIS_SYSCLK_64: 100 return 64000000; 101 case QIXIS_SYSCLK_83: 102 return 83333333; 103 case QIXIS_SYSCLK_100: 104 return 100000000; 105 case QIXIS_SYSCLK_125: 106 return 125000000; 107 case QIXIS_SYSCLK_133: 108 return 133333333; 109 case QIXIS_SYSCLK_150: 110 return 150000000; 111 case QIXIS_SYSCLK_160: 112 return 160000000; 113 case QIXIS_SYSCLK_166: 114 return 166666666; 115 } 116 return 66666666; 117 } 118 119 unsigned long get_board_ddr_clk(void) 120 { 121 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 122 123 switch ((ddrclk_conf & 0x30) >> 4) { 124 case QIXIS_DDRCLK_100: 125 return 100000000; 126 case QIXIS_DDRCLK_125: 127 return 125000000; 128 case QIXIS_DDRCLK_133: 129 return 133333333; 130 } 131 return 66666666; 132 } 133 134 int select_i2c_ch_pca9547(u8 ch) 135 { 136 int ret; 137 138 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 139 if (ret) { 140 puts("PCA: failed to select proper channel\n"); 141 return ret; 142 } 143 144 return 0; 145 } 146 147 int dram_init(void) 148 { 149 /* 150 * When resuming from deep sleep, the I2C channel may not be 151 * in the default channel. So, switch to the default channel 152 * before accessing DDR SPD. 153 */ 154 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 155 gd->ram_size = initdram(0); 156 157 return 0; 158 } 159 160 #ifdef CONFIG_FSL_ESDHC 161 struct fsl_esdhc_cfg esdhc_cfg[1] = { 162 {CONFIG_SYS_FSL_ESDHC_ADDR}, 163 }; 164 165 int board_mmc_init(bd_t *bis) 166 { 167 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 168 169 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 170 } 171 #endif 172 173 int board_early_init_f(void) 174 { 175 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 176 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 177 178 #ifdef CONFIG_TSEC_ENET 179 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 180 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 181 #endif 182 183 #ifdef CONFIG_FSL_IFC 184 init_early_memctl_regs(); 185 #endif 186 187 #ifdef CONFIG_FSL_QSPI 188 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 189 #endif 190 191 /* Workaround for the issue that DDR could not respond to 192 * barrier transaction which is generated by executing DSB/ISB 193 * instruction. Set CCI-400 control override register to 194 * terminate the barrier transaction. After DDR is initialized, 195 * allow barrier transaction to DDR again */ 196 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 197 198 return 0; 199 } 200 201 #ifdef CONFIG_SPL_BUILD 202 void board_init_f(ulong dummy) 203 { 204 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 205 206 #ifdef CONFIG_NAND_BOOT 207 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 208 u32 porsr1, pinctl; 209 210 /* 211 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 212 * NAND boot because IFC signals > IFC_AD7 are not enabled. 213 * This workaround changes RCW source to make all signals enabled. 214 */ 215 porsr1 = in_be32(&gur->porsr1); 216 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 217 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 218 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 219 pinctl); 220 #endif 221 222 /* Clear the BSS */ 223 memset(__bss_start, 0, __bss_end - __bss_start); 224 225 #ifdef CONFIG_FSL_IFC 226 init_early_memctl_regs(); 227 #endif 228 229 get_clocks(); 230 231 preloader_console_init(); 232 233 #ifdef CONFIG_SPL_I2C_SUPPORT 234 i2c_init_all(); 235 #endif 236 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 237 238 dram_init(); 239 240 board_init_r(NULL, 0); 241 } 242 #endif 243 244 int config_board_mux(int ctrl_type) 245 { 246 u8 reg12, reg14; 247 248 reg12 = QIXIS_READ(brdcfg[12]); 249 reg14 = QIXIS_READ(brdcfg[14]); 250 251 switch (ctrl_type) { 252 case MUX_TYPE_CAN: 253 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 254 break; 255 case MUX_TYPE_IIC2: 256 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 257 break; 258 case MUX_TYPE_RGMII: 259 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 260 break; 261 case MUX_TYPE_SAI: 262 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 263 break; 264 case MUX_TYPE_SDHC: 265 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 266 break; 267 case MUX_TYPE_SD_PCI4: 268 reg12 = 0x38; 269 break; 270 case MUX_TYPE_SD_PC_SA_SG_SG: 271 reg12 = 0x01; 272 break; 273 case MUX_TYPE_SD_PC_SA_PC_SG: 274 reg12 = 0x01; 275 break; 276 case MUX_TYPE_SD_PC_SG_SG: 277 reg12 = 0x21; 278 break; 279 default: 280 printf("Wrong mux interface type\n"); 281 return -1; 282 } 283 284 QIXIS_WRITE(brdcfg[12], reg12); 285 QIXIS_WRITE(brdcfg[14], reg14); 286 287 return 0; 288 } 289 290 int config_serdes_mux(void) 291 { 292 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 293 u32 cfg; 294 295 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 296 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 297 298 switch (cfg) { 299 case 0x0: 300 config_board_mux(MUX_TYPE_SD_PCI4); 301 break; 302 case 0x30: 303 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 304 break; 305 case 0x60: 306 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 307 break; 308 case 0x70: 309 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 310 break; 311 default: 312 printf("SRDS1 prtcl:0x%x\n", cfg); 313 break; 314 } 315 316 return 0; 317 } 318 319 int misc_init_r(void) 320 { 321 int conflict_flag; 322 323 /* some signals can not enable simultaneous*/ 324 conflict_flag = 0; 325 if (hwconfig("sdhc")) 326 conflict_flag++; 327 if (hwconfig("iic2")) 328 conflict_flag++; 329 if (conflict_flag > 1) { 330 printf("WARNING: pin conflict !\n"); 331 return 0; 332 } 333 334 conflict_flag = 0; 335 if (hwconfig("rgmii")) 336 conflict_flag++; 337 if (hwconfig("can")) 338 conflict_flag++; 339 if (hwconfig("sai")) 340 conflict_flag++; 341 if (conflict_flag > 1) { 342 printf("WARNING: pin conflict !\n"); 343 return 0; 344 } 345 346 if (hwconfig("can")) 347 config_board_mux(MUX_TYPE_CAN); 348 else if (hwconfig("rgmii")) 349 config_board_mux(MUX_TYPE_RGMII); 350 else if (hwconfig("sai")) 351 config_board_mux(MUX_TYPE_SAI); 352 353 if (hwconfig("iic2")) 354 config_board_mux(MUX_TYPE_IIC2); 355 else if (hwconfig("sdhc")) 356 config_board_mux(MUX_TYPE_SDHC); 357 358 #ifdef CONFIG_FSL_CAAM 359 return sec_init(); 360 #endif 361 return 0; 362 } 363 364 #ifdef CONFIG_LS102XA_NS_ACCESS 365 static struct csu_ns_dev ns_dev[] = { 366 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 367 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 368 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 369 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 370 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 371 { CSU_CSLX_GIC, CSU_ALL_RW }, 372 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 373 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 374 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 375 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 376 { CSU_CSLX_SATA, CSU_ALL_RW }, 377 { CSU_CSLX_USB3, CSU_ALL_RW }, 378 { CSU_CSLX_SERDES, CSU_ALL_RW }, 379 { CSU_CSLX_QDMA, CSU_ALL_RW }, 380 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 381 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 382 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 383 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 384 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 385 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 386 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 387 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 388 { CSU_CSLX_QSPI, CSU_ALL_RW }, 389 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 390 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 391 { CSU_CSLX_IFC, CSU_ALL_RW }, 392 { CSU_CSLX_I2C1, CSU_ALL_RW }, 393 { CSU_CSLX_USB2, CSU_ALL_RW }, 394 { CSU_CSLX_I2C3, CSU_ALL_RW }, 395 { CSU_CSLX_I2C2, CSU_ALL_RW }, 396 { CSU_CSLX_DUART2, CSU_ALL_RW }, 397 { CSU_CSLX_DUART1, CSU_ALL_RW }, 398 { CSU_CSLX_WDT2, CSU_ALL_RW }, 399 { CSU_CSLX_WDT1, CSU_ALL_RW }, 400 { CSU_CSLX_EDMA, CSU_ALL_RW }, 401 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 402 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 403 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 404 { CSU_CSLX_DDR, CSU_ALL_RW }, 405 { CSU_CSLX_QUICC, CSU_ALL_RW }, 406 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 407 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 408 { CSU_CSLX_SFP, CSU_ALL_RW }, 409 { CSU_CSLX_TMU, CSU_ALL_RW }, 410 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 411 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 412 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 413 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 414 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 415 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 416 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 417 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 418 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 419 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 420 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 421 { CSU_CSLX_CSU, CSU_ALL_RW }, 422 { CSU_CSLX_ASRC, CSU_ALL_RW }, 423 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 424 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 425 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 426 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 427 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 428 { CSU_CSLX_SAI2, CSU_ALL_RW }, 429 { CSU_CSLX_SAI1, CSU_ALL_RW }, 430 { CSU_CSLX_SAI4, CSU_ALL_RW }, 431 { CSU_CSLX_SAI3, CSU_ALL_RW }, 432 { CSU_CSLX_FTM2, CSU_ALL_RW }, 433 { CSU_CSLX_FTM1, CSU_ALL_RW }, 434 { CSU_CSLX_FTM4, CSU_ALL_RW }, 435 { CSU_CSLX_FTM3, CSU_ALL_RW }, 436 { CSU_CSLX_FTM6, CSU_ALL_RW }, 437 { CSU_CSLX_FTM5, CSU_ALL_RW }, 438 { CSU_CSLX_FTM8, CSU_ALL_RW }, 439 { CSU_CSLX_FTM7, CSU_ALL_RW }, 440 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 441 { CSU_CSLX_EPU, CSU_ALL_RW }, 442 { CSU_CSLX_GDI, CSU_ALL_RW }, 443 { CSU_CSLX_DDI, CSU_ALL_RW }, 444 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 445 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 446 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 447 }; 448 #endif 449 450 struct smmu_stream_id dev_stream_id[] = { 451 { 0x100, 0x01, "ETSEC MAC1" }, 452 { 0x104, 0x02, "ETSEC MAC2" }, 453 { 0x108, 0x03, "ETSEC MAC3" }, 454 { 0x10c, 0x04, "PEX1" }, 455 { 0x110, 0x05, "PEX2" }, 456 { 0x114, 0x06, "qDMA" }, 457 { 0x118, 0x07, "SATA" }, 458 { 0x11c, 0x08, "USB3" }, 459 { 0x120, 0x09, "QE" }, 460 { 0x124, 0x0a, "eSDHC" }, 461 { 0x128, 0x0b, "eMA" }, 462 { 0x14c, 0x0c, "2D-ACE" }, 463 { 0x150, 0x0d, "USB2" }, 464 { 0x18c, 0x0e, "DEBUG" }, 465 }; 466 467 int board_init(void) 468 { 469 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 470 471 /* Set CCI-400 control override register to 472 * enable barrier transaction */ 473 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 474 /* 475 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register 476 * All transactions are treated as non-shareable 477 */ 478 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 479 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 480 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 481 482 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 483 484 #ifndef CONFIG_SYS_FSL_NO_SERDES 485 fsl_serdes_init(); 486 config_serdes_mux(); 487 #endif 488 489 ls102xa_config_smmu_stream_id(dev_stream_id, 490 ARRAY_SIZE(dev_stream_id)); 491 492 #ifdef CONFIG_LS102XA_NS_ACCESS 493 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 494 #endif 495 496 #ifdef CONFIG_U_QE 497 u_qe_init(); 498 #endif 499 500 return 0; 501 } 502 503 int ft_board_setup(void *blob, bd_t *bd) 504 { 505 ft_cpu_setup(blob, bd); 506 507 #ifdef CONFIG_PCIE_LAYERSCAPE 508 ft_pcie_setup(blob, bd); 509 #endif 510 511 return 0; 512 } 513 514 u8 flash_read8(void *addr) 515 { 516 return __raw_readb(addr + 1); 517 } 518 519 void flash_write16(u16 val, void *addr) 520 { 521 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 522 523 __raw_writew(shftval, addr); 524 } 525 526 u16 flash_read16(void *addr) 527 { 528 u16 val = __raw_readw(addr); 529 530 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 531 } 532