1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <fsl_ifc.h>
16 #include <fsl_sec.h>
17 
18 #include "../common/qixis.h"
19 #include "ls1021aqds_qixis.h"
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 enum {
24 	MUX_TYPE_SD_PCI4,
25 	MUX_TYPE_SD_PC_SA_SG_SG,
26 	MUX_TYPE_SD_PC_SA_PC_SG,
27 	MUX_TYPE_SD_PC_SG_SG,
28 };
29 
30 int checkboard(void)
31 {
32 	char buf[64];
33 	u8 sw;
34 
35 	puts("Board: LS1021AQDS\n");
36 
37 	sw = QIXIS_READ(brdcfg[0]);
38 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
39 
40 	if (sw < 0x8)
41 		printf("vBank: %d\n", sw);
42 	else if (sw == 0x8)
43 		puts("PromJet\n");
44 	else if (sw == 0x9)
45 		puts("NAND\n");
46 	else if (sw == 0x15)
47 		printf("IFCCard\n");
48 	else
49 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
50 
51 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
52 	       QIXIS_READ(id), QIXIS_READ(arch));
53 
54 	printf("FPGA:  v%d (%s), build %d\n",
55 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
56 	       (int)qixis_read_minor());
57 
58 	return 0;
59 }
60 
61 unsigned long get_board_sys_clk(void)
62 {
63 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
64 
65 	switch (sysclk_conf & 0x0f) {
66 	case QIXIS_SYSCLK_64:
67 		return 64000000;
68 	case QIXIS_SYSCLK_83:
69 		return 83333333;
70 	case QIXIS_SYSCLK_100:
71 		return 100000000;
72 	case QIXIS_SYSCLK_125:
73 		return 125000000;
74 	case QIXIS_SYSCLK_133:
75 		return 133333333;
76 	case QIXIS_SYSCLK_150:
77 		return 150000000;
78 	case QIXIS_SYSCLK_160:
79 		return 160000000;
80 	case QIXIS_SYSCLK_166:
81 		return 166666666;
82 	}
83 	return 66666666;
84 }
85 
86 unsigned long get_board_ddr_clk(void)
87 {
88 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
89 
90 	switch ((ddrclk_conf & 0x30) >> 4) {
91 	case QIXIS_DDRCLK_100:
92 		return 100000000;
93 	case QIXIS_DDRCLK_125:
94 		return 125000000;
95 	case QIXIS_DDRCLK_133:
96 		return 133333333;
97 	}
98 	return 66666666;
99 }
100 
101 int dram_init(void)
102 {
103 	gd->ram_size = initdram(0);
104 
105 	return 0;
106 }
107 
108 #ifdef CONFIG_FSL_ESDHC
109 struct fsl_esdhc_cfg esdhc_cfg[1] = {
110 	{CONFIG_SYS_FSL_ESDHC_ADDR},
111 };
112 
113 int board_mmc_init(bd_t *bis)
114 {
115 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
116 
117 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
118 }
119 #endif
120 
121 int select_i2c_ch_pca9547(u8 ch)
122 {
123 	int ret;
124 
125 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
126 	if (ret) {
127 		puts("PCA: failed to select proper channel\n");
128 		return ret;
129 	}
130 
131 	return 0;
132 }
133 
134 int board_early_init_f(void)
135 {
136 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
137 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
138 
139 #ifdef CONFIG_TSEC_ENET
140 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
141 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
142 	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
143 #endif
144 
145 #ifdef CONFIG_FSL_IFC
146 	init_early_memctl_regs();
147 #endif
148 
149 	/* Workaround for the issue that DDR could not respond to
150 	 * barrier transaction which is generated by executing DSB/ISB
151 	 * instruction. Set CCI-400 control override register to
152 	 * terminate the barrier transaction. After DDR is initialized,
153 	 * allow barrier transaction to DDR again */
154 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
155 
156 	return 0;
157 }
158 
159 int config_board_mux(int ctrl_type)
160 {
161 	u8 reg12;
162 
163 	reg12 = QIXIS_READ(brdcfg[12]);
164 
165 	switch (ctrl_type) {
166 	case MUX_TYPE_SD_PCI4:
167 		reg12 = 0x38;
168 		break;
169 	case MUX_TYPE_SD_PC_SA_SG_SG:
170 		reg12 = 0x01;
171 		break;
172 	case MUX_TYPE_SD_PC_SA_PC_SG:
173 		reg12 = 0x01;
174 		break;
175 	case MUX_TYPE_SD_PC_SG_SG:
176 		reg12 = 0x21;
177 		break;
178 	default:
179 		printf("Wrong mux interface type\n");
180 		return -1;
181 	}
182 
183 	QIXIS_WRITE(brdcfg[12], reg12);
184 
185 	return 0;
186 }
187 
188 int config_serdes_mux(void)
189 {
190 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
191 	u32 cfg;
192 
193 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
194 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
195 
196 	switch (cfg) {
197 	case 0x0:
198 		config_board_mux(MUX_TYPE_SD_PCI4);
199 		break;
200 	case 0x30:
201 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
202 		break;
203 	case 0x60:
204 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
205 		break;
206 	case 0x70:
207 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
208 		break;
209 	default:
210 		printf("SRDS1 prtcl:0x%x\n", cfg);
211 		break;
212 	}
213 
214 	return 0;
215 }
216 
217 #if defined(CONFIG_MISC_INIT_R)
218 int misc_init_r(void)
219 {
220 #ifdef CONFIG_FSL_CAAM
221 	return sec_init();
222 #endif
223 }
224 #endif
225 
226 int board_init(void)
227 {
228 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
229 
230 	/* Set CCI-400 control override register to
231 	 * enable barrier transaction */
232 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
233 
234 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
235 
236 #ifndef CONFIG_SYS_FSL_NO_SERDES
237 	fsl_serdes_init();
238 	config_serdes_mux();
239 #endif
240 	return 0;
241 }
242 
243 void ft_board_setup(void *blob, bd_t *bd)
244 {
245 	ft_cpu_setup(blob, bd);
246 }
247 
248 u8 flash_read8(void *addr)
249 {
250 	return __raw_readb(addr + 1);
251 }
252 
253 void flash_write16(u16 val, void *addr)
254 {
255 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
256 
257 	__raw_writew(shftval, addr);
258 }
259 
260 u16 flash_read16(void *addr)
261 {
262 	u16 val = __raw_readw(addr);
263 
264 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
265 }
266