1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_soc.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_csu.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_sec.h>
22 #include <spl.h>
23 #include <fsl_devdis.h>
24 #include <fsl_validate.h>
25 
26 #include "../common/sleep.h"
27 #include "../common/qixis.h"
28 #include "ls1021aqds_qixis.h"
29 #ifdef CONFIG_U_QE
30 #include <fsl_qe.h>
31 #endif
32 
33 #define PIN_MUX_SEL_CAN		0x03
34 #define PIN_MUX_SEL_IIC2	0xa0
35 #define PIN_MUX_SEL_RGMII	0x00
36 #define PIN_MUX_SEL_SAI		0x0c
37 #define PIN_MUX_SEL_SDHC	0x00
38 
39 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
40 #define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 enum {
44 	MUX_TYPE_CAN,
45 	MUX_TYPE_IIC2,
46 	MUX_TYPE_RGMII,
47 	MUX_TYPE_SAI,
48 	MUX_TYPE_SDHC,
49 	MUX_TYPE_SD_PCI4,
50 	MUX_TYPE_SD_PC_SA_SG_SG,
51 	MUX_TYPE_SD_PC_SA_PC_SG,
52 	MUX_TYPE_SD_PC_SG_SG,
53 };
54 
55 enum {
56 	GE0_CLK125,
57 	GE2_CLK125,
58 	GE1_CLK125,
59 };
60 
61 int checkboard(void)
62 {
63 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
64 	char buf[64];
65 #endif
66 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
67 	u8 sw;
68 #endif
69 
70 	puts("Board: LS1021AQDS\n");
71 
72 #ifdef CONFIG_SD_BOOT
73 	puts("SD\n");
74 #elif CONFIG_QSPI_BOOT
75 	puts("QSPI\n");
76 #else
77 	sw = QIXIS_READ(brdcfg[0]);
78 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
79 
80 	if (sw < 0x8)
81 		printf("vBank: %d\n", sw);
82 	else if (sw == 0x8)
83 		puts("PromJet\n");
84 	else if (sw == 0x9)
85 		puts("NAND\n");
86 	else if (sw == 0x15)
87 		printf("IFCCard\n");
88 	else
89 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
90 #endif
91 
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
93 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
94 	       QIXIS_READ(id), QIXIS_READ(arch));
95 
96 	printf("FPGA:  v%d (%s), build %d\n",
97 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
98 	       (int)qixis_read_minor());
99 #endif
100 
101 	return 0;
102 }
103 
104 unsigned long get_board_sys_clk(void)
105 {
106 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
107 
108 	switch (sysclk_conf & 0x0f) {
109 	case QIXIS_SYSCLK_64:
110 		return 64000000;
111 	case QIXIS_SYSCLK_83:
112 		return 83333333;
113 	case QIXIS_SYSCLK_100:
114 		return 100000000;
115 	case QIXIS_SYSCLK_125:
116 		return 125000000;
117 	case QIXIS_SYSCLK_133:
118 		return 133333333;
119 	case QIXIS_SYSCLK_150:
120 		return 150000000;
121 	case QIXIS_SYSCLK_160:
122 		return 160000000;
123 	case QIXIS_SYSCLK_166:
124 		return 166666666;
125 	}
126 	return 66666666;
127 }
128 
129 unsigned long get_board_ddr_clk(void)
130 {
131 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
132 
133 	switch ((ddrclk_conf & 0x30) >> 4) {
134 	case QIXIS_DDRCLK_100:
135 		return 100000000;
136 	case QIXIS_DDRCLK_125:
137 		return 125000000;
138 	case QIXIS_DDRCLK_133:
139 		return 133333333;
140 	}
141 	return 66666666;
142 }
143 
144 int select_i2c_ch_pca9547(u8 ch)
145 {
146 	int ret;
147 
148 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
149 	if (ret) {
150 		puts("PCA: failed to select proper channel\n");
151 		return ret;
152 	}
153 
154 	return 0;
155 }
156 
157 int dram_init(void)
158 {
159 	/*
160 	 * When resuming from deep sleep, the I2C channel may not be
161 	 * in the default channel. So, switch to the default channel
162 	 * before accessing DDR SPD.
163 	 */
164 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
165 	gd->ram_size = initdram(0);
166 
167 	return 0;
168 }
169 
170 #ifdef CONFIG_FSL_ESDHC
171 struct fsl_esdhc_cfg esdhc_cfg[1] = {
172 	{CONFIG_SYS_FSL_ESDHC_ADDR},
173 };
174 
175 int board_mmc_init(bd_t *bis)
176 {
177 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
178 
179 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
180 }
181 #endif
182 
183 int board_early_init_f(void)
184 {
185 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
186 
187 #ifdef CONFIG_TSEC_ENET
188 	/* clear BD & FR bits for BE BD's and frame data */
189 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
190 #endif
191 
192 #ifdef CONFIG_FSL_IFC
193 	init_early_memctl_regs();
194 #endif
195 
196 	arch_soc_init();
197 
198 #if defined(CONFIG_DEEP_SLEEP)
199 	if (is_warm_boot())
200 		fsl_dp_disable_console();
201 #endif
202 
203 	return 0;
204 }
205 
206 #ifdef CONFIG_SPL_BUILD
207 void board_init_f(ulong dummy)
208 {
209 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
210 	unsigned int major;
211 
212 #ifdef CONFIG_NAND_BOOT
213 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
214 	u32 porsr1, pinctl;
215 
216 	/*
217 	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
218 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
219 	 * This workaround changes RCW source to make all signals enabled.
220 	 */
221 	porsr1 = in_be32(&gur->porsr1);
222 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
223 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
224 	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
225 		 pinctl);
226 #endif
227 
228 	/* Clear the BSS */
229 	memset(__bss_start, 0, __bss_end - __bss_start);
230 
231 #ifdef CONFIG_FSL_IFC
232 	init_early_memctl_regs();
233 #endif
234 
235 	get_clocks();
236 
237 #if defined(CONFIG_DEEP_SLEEP)
238 	if (is_warm_boot())
239 		fsl_dp_disable_console();
240 #endif
241 
242 	preloader_console_init();
243 
244 #ifdef CONFIG_SPL_I2C_SUPPORT
245 	i2c_init_all();
246 #endif
247 
248 	major = get_soc_major_rev();
249 	if (major == SOC_MAJOR_VER_1_0)
250 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
251 
252 	dram_init();
253 
254 	/* Allow OCRAM access permission as R/W */
255 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
256 	enable_layerscape_ns_access();
257 #endif
258 
259 	board_init_r(NULL, 0);
260 }
261 #endif
262 
263 void config_etseccm_source(int etsec_gtx_125_mux)
264 {
265 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
266 
267 	switch (etsec_gtx_125_mux) {
268 	case GE0_CLK125:
269 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
270 		debug("etseccm set to GE0_CLK125\n");
271 		break;
272 
273 	case GE2_CLK125:
274 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
275 		debug("etseccm set to GE2_CLK125\n");
276 		break;
277 
278 	case GE1_CLK125:
279 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
280 		debug("etseccm set to GE1_CLK125\n");
281 		break;
282 
283 	default:
284 		printf("Error! trying to set etseccm to invalid value\n");
285 		break;
286 	}
287 }
288 
289 int config_board_mux(int ctrl_type)
290 {
291 	u8 reg12, reg14;
292 
293 	reg12 = QIXIS_READ(brdcfg[12]);
294 	reg14 = QIXIS_READ(brdcfg[14]);
295 
296 	switch (ctrl_type) {
297 	case MUX_TYPE_CAN:
298 		config_etseccm_source(GE2_CLK125);
299 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
300 		break;
301 	case MUX_TYPE_IIC2:
302 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
303 		break;
304 	case MUX_TYPE_RGMII:
305 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
306 		break;
307 	case MUX_TYPE_SAI:
308 		config_etseccm_source(GE2_CLK125);
309 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
310 		break;
311 	case MUX_TYPE_SDHC:
312 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
313 		break;
314 	case MUX_TYPE_SD_PCI4:
315 		reg12 = 0x38;
316 		break;
317 	case MUX_TYPE_SD_PC_SA_SG_SG:
318 		reg12 = 0x01;
319 		break;
320 	case MUX_TYPE_SD_PC_SA_PC_SG:
321 		reg12 = 0x01;
322 		break;
323 	case MUX_TYPE_SD_PC_SG_SG:
324 		reg12 = 0x21;
325 		break;
326 	default:
327 		printf("Wrong mux interface type\n");
328 		return -1;
329 	}
330 
331 	QIXIS_WRITE(brdcfg[12], reg12);
332 	QIXIS_WRITE(brdcfg[14], reg14);
333 
334 	return 0;
335 }
336 
337 int config_serdes_mux(void)
338 {
339 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
340 	u32 cfg;
341 
342 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
343 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
344 
345 	switch (cfg) {
346 	case 0x0:
347 		config_board_mux(MUX_TYPE_SD_PCI4);
348 		break;
349 	case 0x30:
350 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
351 		break;
352 	case 0x60:
353 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
354 		break;
355 	case 0x70:
356 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
357 		break;
358 	default:
359 		printf("SRDS1 prtcl:0x%x\n", cfg);
360 		break;
361 	}
362 
363 	return 0;
364 }
365 
366 #ifdef CONFIG_BOARD_LATE_INIT
367 int board_late_init(void)
368 {
369 #ifdef CONFIG_SCSI_AHCI_PLAT
370 	ls1021a_sata_init();
371 #endif
372 #ifdef CONFIG_CHAIN_OF_TRUST
373 	fsl_setenv_chain_of_trust();
374 #endif
375 
376 	return 0;
377 }
378 #endif
379 
380 int misc_init_r(void)
381 {
382 	int conflict_flag;
383 
384 	/* some signals can not enable simultaneous*/
385 	conflict_flag = 0;
386 	if (hwconfig("sdhc"))
387 		conflict_flag++;
388 	if (hwconfig("iic2"))
389 		conflict_flag++;
390 	if (conflict_flag > 1) {
391 		printf("WARNING: pin conflict !\n");
392 		return 0;
393 	}
394 
395 	conflict_flag = 0;
396 	if (hwconfig("rgmii"))
397 		conflict_flag++;
398 	if (hwconfig("can"))
399 		conflict_flag++;
400 	if (hwconfig("sai"))
401 		conflict_flag++;
402 	if (conflict_flag > 1) {
403 		printf("WARNING: pin conflict !\n");
404 		return 0;
405 	}
406 
407 	if (hwconfig("can"))
408 		config_board_mux(MUX_TYPE_CAN);
409 	else if (hwconfig("rgmii"))
410 		config_board_mux(MUX_TYPE_RGMII);
411 	else if (hwconfig("sai"))
412 		config_board_mux(MUX_TYPE_SAI);
413 
414 	if (hwconfig("iic2"))
415 		config_board_mux(MUX_TYPE_IIC2);
416 	else if (hwconfig("sdhc"))
417 		config_board_mux(MUX_TYPE_SDHC);
418 
419 #ifdef CONFIG_FSL_DEVICE_DISABLE
420 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
421 #endif
422 #ifdef CONFIG_FSL_CAAM
423 	return sec_init();
424 #endif
425 	return 0;
426 }
427 
428 int board_init(void)
429 {
430 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
431 	unsigned int major;
432 
433 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
434 	erratum_a010315();
435 #endif
436 
437 	major = get_soc_major_rev();
438 	if (major == SOC_MAJOR_VER_1_0) {
439 		/* Set CCI-400 control override register to
440 		 * enable barrier transaction */
441 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
442 	}
443 
444 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
445 
446 #ifndef CONFIG_SYS_FSL_NO_SERDES
447 	fsl_serdes_init();
448 	config_serdes_mux();
449 #endif
450 
451 	ls102xa_smmu_stream_id_init();
452 
453 #ifdef CONFIG_U_QE
454 	u_qe_init();
455 #endif
456 
457 	return 0;
458 }
459 
460 #if defined(CONFIG_DEEP_SLEEP)
461 void board_sleep_prepare(void)
462 {
463 	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
464 	unsigned int major;
465 
466 	major = get_soc_major_rev();
467 	if (major == SOC_MAJOR_VER_1_0) {
468 		/* Set CCI-400 control override register to
469 		 * enable barrier transaction */
470 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
471 	}
472 
473 
474 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
475 	enable_layerscape_ns_access();
476 #endif
477 }
478 #endif
479 
480 int ft_board_setup(void *blob, bd_t *bd)
481 {
482 	ft_cpu_setup(blob, bd);
483 
484 #ifdef CONFIG_PCI
485 	ft_pci_setup(blob, bd);
486 #endif
487 
488 	return 0;
489 }
490 
491 u8 flash_read8(void *addr)
492 {
493 	return __raw_readb(addr + 1);
494 }
495 
496 void flash_write16(u16 val, void *addr)
497 {
498 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
499 
500 	__raw_writew(shftval, addr);
501 }
502 
503 u16 flash_read16(void *addr)
504 {
505 	u16 val = __raw_readw(addr);
506 
507 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
508 }
509