1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <hwconfig.h>
15 #include <mmc.h>
16 #include <fsl_csu.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_ifc.h>
19 #include <fsl_sec.h>
20 #include <spl.h>
21 #include <fsl_devdis.h>
22 #include <fsl_validate.h>
23 #include <fsl_ddr.h>
24 #include "../common/sleep.h"
25 #include "../common/qixis.h"
26 #include "ls1021aqds_qixis.h"
27 #ifdef CONFIG_U_QE
28 #include <fsl_qe.h>
29 #endif
30 
31 #define PIN_MUX_SEL_CAN		0x03
32 #define PIN_MUX_SEL_IIC2	0xa0
33 #define PIN_MUX_SEL_RGMII	0x00
34 #define PIN_MUX_SEL_SAI		0x0c
35 #define PIN_MUX_SEL_SDHC	0x00
36 
37 #define SET_SDHC_MUX_SEL(reg, value)	((reg & 0x0f) | value)
38 #define SET_EC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
39 enum {
40 	MUX_TYPE_CAN,
41 	MUX_TYPE_IIC2,
42 	MUX_TYPE_RGMII,
43 	MUX_TYPE_SAI,
44 	MUX_TYPE_SDHC,
45 	MUX_TYPE_SD_PCI4,
46 	MUX_TYPE_SD_PC_SA_SG_SG,
47 	MUX_TYPE_SD_PC_SA_PC_SG,
48 	MUX_TYPE_SD_PC_SG_SG,
49 };
50 
51 enum {
52 	GE0_CLK125,
53 	GE2_CLK125,
54 	GE1_CLK125,
55 };
56 
57 int checkboard(void)
58 {
59 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
60 	char buf[64];
61 #endif
62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
63 	u8 sw;
64 #endif
65 
66 	puts("Board: LS1021AQDS\n");
67 
68 #ifdef CONFIG_SD_BOOT
69 	puts("SD\n");
70 #elif CONFIG_QSPI_BOOT
71 	puts("QSPI\n");
72 #else
73 	sw = QIXIS_READ(brdcfg[0]);
74 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
75 
76 	if (sw < 0x8)
77 		printf("vBank: %d\n", sw);
78 	else if (sw == 0x8)
79 		puts("PromJet\n");
80 	else if (sw == 0x9)
81 		puts("NAND\n");
82 	else if (sw == 0x15)
83 		printf("IFCCard\n");
84 	else
85 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
86 #endif
87 
88 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
89 	printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
90 	       QIXIS_READ(id), QIXIS_READ(arch));
91 
92 	printf("FPGA:  v%d (%s), build %d\n",
93 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
94 	       (int)qixis_read_minor());
95 #endif
96 
97 	return 0;
98 }
99 
100 unsigned long get_board_sys_clk(void)
101 {
102 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
103 
104 	switch (sysclk_conf & 0x0f) {
105 	case QIXIS_SYSCLK_64:
106 		return 64000000;
107 	case QIXIS_SYSCLK_83:
108 		return 83333333;
109 	case QIXIS_SYSCLK_100:
110 		return 100000000;
111 	case QIXIS_SYSCLK_125:
112 		return 125000000;
113 	case QIXIS_SYSCLK_133:
114 		return 133333333;
115 	case QIXIS_SYSCLK_150:
116 		return 150000000;
117 	case QIXIS_SYSCLK_160:
118 		return 160000000;
119 	case QIXIS_SYSCLK_166:
120 		return 166666666;
121 	}
122 	return 66666666;
123 }
124 
125 unsigned long get_board_ddr_clk(void)
126 {
127 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
128 
129 	switch ((ddrclk_conf & 0x30) >> 4) {
130 	case QIXIS_DDRCLK_100:
131 		return 100000000;
132 	case QIXIS_DDRCLK_125:
133 		return 125000000;
134 	case QIXIS_DDRCLK_133:
135 		return 133333333;
136 	}
137 	return 66666666;
138 }
139 
140 int select_i2c_ch_pca9547(u8 ch)
141 {
142 	int ret;
143 
144 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
145 	if (ret) {
146 		puts("PCA: failed to select proper channel\n");
147 		return ret;
148 	}
149 
150 	return 0;
151 }
152 
153 int dram_init(void)
154 {
155 	/*
156 	 * When resuming from deep sleep, the I2C channel may not be
157 	 * in the default channel. So, switch to the default channel
158 	 * before accessing DDR SPD.
159 	 */
160 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 	return fsl_initdram();
162 }
163 
164 #ifdef CONFIG_FSL_ESDHC
165 struct fsl_esdhc_cfg esdhc_cfg[1] = {
166 	{CONFIG_SYS_FSL_ESDHC_ADDR},
167 };
168 
169 int board_mmc_init(bd_t *bis)
170 {
171 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
172 
173 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
174 }
175 #endif
176 
177 int board_early_init_f(void)
178 {
179 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
180 
181 #ifdef CONFIG_TSEC_ENET
182 	/* clear BD & FR bits for BE BD's and frame data */
183 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
184 #endif
185 
186 #ifdef CONFIG_FSL_IFC
187 	init_early_memctl_regs();
188 #endif
189 
190 	arch_soc_init();
191 
192 #if defined(CONFIG_DEEP_SLEEP)
193 	if (is_warm_boot())
194 		fsl_dp_disable_console();
195 #endif
196 
197 	return 0;
198 }
199 
200 #ifdef CONFIG_SPL_BUILD
201 void board_init_f(ulong dummy)
202 {
203 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
204 					CONFIG_SYS_CCI400_OFFSET);
205 	unsigned int major;
206 
207 #ifdef CONFIG_NAND_BOOT
208 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
209 	u32 porsr1, pinctl;
210 
211 	/*
212 	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
213 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
214 	 * This workaround changes RCW source to make all signals enabled.
215 	 */
216 	porsr1 = in_be32(&gur->porsr1);
217 	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
218 		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
219 	out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
220 		 pinctl);
221 #endif
222 
223 	/* Clear the BSS */
224 	memset(__bss_start, 0, __bss_end - __bss_start);
225 
226 #ifdef CONFIG_FSL_IFC
227 	init_early_memctl_regs();
228 #endif
229 
230 	get_clocks();
231 
232 #if defined(CONFIG_DEEP_SLEEP)
233 	if (is_warm_boot())
234 		fsl_dp_disable_console();
235 #endif
236 
237 	preloader_console_init();
238 
239 #ifdef CONFIG_SPL_I2C_SUPPORT
240 	i2c_init_all();
241 #endif
242 
243 	major = get_soc_major_rev();
244 	if (major == SOC_MAJOR_VER_1_0)
245 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
246 
247 	dram_init();
248 
249 	/* Allow OCRAM access permission as R/W */
250 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
251 	enable_layerscape_ns_access();
252 #endif
253 
254 	board_init_r(NULL, 0);
255 }
256 #endif
257 
258 void config_etseccm_source(int etsec_gtx_125_mux)
259 {
260 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
261 
262 	switch (etsec_gtx_125_mux) {
263 	case GE0_CLK125:
264 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
265 		debug("etseccm set to GE0_CLK125\n");
266 		break;
267 
268 	case GE2_CLK125:
269 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
270 		debug("etseccm set to GE2_CLK125\n");
271 		break;
272 
273 	case GE1_CLK125:
274 		out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
275 		debug("etseccm set to GE1_CLK125\n");
276 		break;
277 
278 	default:
279 		printf("Error! trying to set etseccm to invalid value\n");
280 		break;
281 	}
282 }
283 
284 int config_board_mux(int ctrl_type)
285 {
286 	u8 reg12, reg14;
287 
288 	reg12 = QIXIS_READ(brdcfg[12]);
289 	reg14 = QIXIS_READ(brdcfg[14]);
290 
291 	switch (ctrl_type) {
292 	case MUX_TYPE_CAN:
293 		config_etseccm_source(GE2_CLK125);
294 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
295 		break;
296 	case MUX_TYPE_IIC2:
297 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
298 		break;
299 	case MUX_TYPE_RGMII:
300 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
301 		break;
302 	case MUX_TYPE_SAI:
303 		config_etseccm_source(GE2_CLK125);
304 		reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
305 		break;
306 	case MUX_TYPE_SDHC:
307 		reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
308 		break;
309 	case MUX_TYPE_SD_PCI4:
310 		reg12 = 0x38;
311 		break;
312 	case MUX_TYPE_SD_PC_SA_SG_SG:
313 		reg12 = 0x01;
314 		break;
315 	case MUX_TYPE_SD_PC_SA_PC_SG:
316 		reg12 = 0x01;
317 		break;
318 	case MUX_TYPE_SD_PC_SG_SG:
319 		reg12 = 0x21;
320 		break;
321 	default:
322 		printf("Wrong mux interface type\n");
323 		return -1;
324 	}
325 
326 	QIXIS_WRITE(brdcfg[12], reg12);
327 	QIXIS_WRITE(brdcfg[14], reg14);
328 
329 	return 0;
330 }
331 
332 int config_serdes_mux(void)
333 {
334 	struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
335 	u32 cfg;
336 
337 	cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
338 	cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
339 
340 	switch (cfg) {
341 	case 0x0:
342 		config_board_mux(MUX_TYPE_SD_PCI4);
343 		break;
344 	case 0x30:
345 		config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
346 		break;
347 	case 0x60:
348 		config_board_mux(MUX_TYPE_SD_PC_SG_SG);
349 		break;
350 	case 0x70:
351 		config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
352 		break;
353 	default:
354 		printf("SRDS1 prtcl:0x%x\n", cfg);
355 		break;
356 	}
357 
358 	return 0;
359 }
360 
361 #ifdef CONFIG_BOARD_LATE_INIT
362 int board_late_init(void)
363 {
364 #ifdef CONFIG_CHAIN_OF_TRUST
365 	fsl_setenv_chain_of_trust();
366 #endif
367 
368 	return 0;
369 }
370 #endif
371 
372 int misc_init_r(void)
373 {
374 	int conflict_flag;
375 
376 	/* some signals can not enable simultaneous*/
377 	conflict_flag = 0;
378 	if (hwconfig("sdhc"))
379 		conflict_flag++;
380 	if (hwconfig("iic2"))
381 		conflict_flag++;
382 	if (conflict_flag > 1) {
383 		printf("WARNING: pin conflict !\n");
384 		return 0;
385 	}
386 
387 	conflict_flag = 0;
388 	if (hwconfig("rgmii"))
389 		conflict_flag++;
390 	if (hwconfig("can"))
391 		conflict_flag++;
392 	if (hwconfig("sai"))
393 		conflict_flag++;
394 	if (conflict_flag > 1) {
395 		printf("WARNING: pin conflict !\n");
396 		return 0;
397 	}
398 
399 	if (hwconfig("can"))
400 		config_board_mux(MUX_TYPE_CAN);
401 	else if (hwconfig("rgmii"))
402 		config_board_mux(MUX_TYPE_RGMII);
403 	else if (hwconfig("sai"))
404 		config_board_mux(MUX_TYPE_SAI);
405 
406 	if (hwconfig("iic2"))
407 		config_board_mux(MUX_TYPE_IIC2);
408 	else if (hwconfig("sdhc"))
409 		config_board_mux(MUX_TYPE_SDHC);
410 
411 #ifdef CONFIG_FSL_DEVICE_DISABLE
412 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
413 #endif
414 #ifdef CONFIG_FSL_CAAM
415 	return sec_init();
416 #endif
417 	return 0;
418 }
419 
420 int board_init(void)
421 {
422 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
423 					CONFIG_SYS_CCI400_OFFSET);
424 	unsigned int major;
425 
426 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
427 	erratum_a010315();
428 #endif
429 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
430 	erratum_a009942_check_cpo();
431 #endif
432 	major = get_soc_major_rev();
433 	if (major == SOC_MAJOR_VER_1_0) {
434 		/* Set CCI-400 control override register to
435 		 * enable barrier transaction */
436 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
437 	}
438 
439 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
440 
441 #ifndef CONFIG_SYS_FSL_NO_SERDES
442 	fsl_serdes_init();
443 	config_serdes_mux();
444 #endif
445 
446 	ls102xa_smmu_stream_id_init();
447 
448 #ifdef CONFIG_U_QE
449 	u_qe_init();
450 #endif
451 
452 	return 0;
453 }
454 
455 #if defined(CONFIG_DEEP_SLEEP)
456 void board_sleep_prepare(void)
457 {
458 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
459 						CONFIG_SYS_CCI400_OFFSET);
460 	unsigned int major;
461 
462 	major = get_soc_major_rev();
463 	if (major == SOC_MAJOR_VER_1_0) {
464 		/* Set CCI-400 control override register to
465 		 * enable barrier transaction */
466 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
467 	}
468 
469 
470 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
471 	enable_layerscape_ns_access();
472 #endif
473 }
474 #endif
475 
476 int ft_board_setup(void *blob, bd_t *bd)
477 {
478 	ft_cpu_setup(blob, bd);
479 
480 #ifdef CONFIG_PCI
481 	ft_pci_setup(blob, bd);
482 #endif
483 
484 	return 0;
485 }
486 
487 u8 flash_read8(void *addr)
488 {
489 	return __raw_readb(addr + 1);
490 }
491 
492 void flash_write16(u16 val, void *addr)
493 {
494 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
495 
496 	__raw_writew(shftval, addr);
497 }
498 
499 u16 flash_read16(void *addr)
500 {
501 	u16 val = __raw_readw(addr);
502 
503 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
504 }
505