1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <fsl_ifc.h> 16 #include <fsl_sec.h> 17 18 #include "../common/qixis.h" 19 #include "ls1021aqds_qixis.h" 20 #ifdef CONFIG_U_QE 21 #include "../../../drivers/qe/qe.h" 22 #endif 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 enum { 27 MUX_TYPE_SD_PCI4, 28 MUX_TYPE_SD_PC_SA_SG_SG, 29 MUX_TYPE_SD_PC_SA_PC_SG, 30 MUX_TYPE_SD_PC_SG_SG, 31 }; 32 33 int checkboard(void) 34 { 35 char buf[64]; 36 u8 sw; 37 38 puts("Board: LS1021AQDS\n"); 39 40 sw = QIXIS_READ(brdcfg[0]); 41 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 42 43 if (sw < 0x8) 44 printf("vBank: %d\n", sw); 45 else if (sw == 0x8) 46 puts("PromJet\n"); 47 else if (sw == 0x9) 48 puts("NAND\n"); 49 else if (sw == 0x15) 50 printf("IFCCard\n"); 51 else 52 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 53 54 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 55 QIXIS_READ(id), QIXIS_READ(arch)); 56 57 printf("FPGA: v%d (%s), build %d\n", 58 (int)QIXIS_READ(scver), qixis_read_tag(buf), 59 (int)qixis_read_minor()); 60 61 return 0; 62 } 63 64 unsigned long get_board_sys_clk(void) 65 { 66 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 67 68 switch (sysclk_conf & 0x0f) { 69 case QIXIS_SYSCLK_64: 70 return 64000000; 71 case QIXIS_SYSCLK_83: 72 return 83333333; 73 case QIXIS_SYSCLK_100: 74 return 100000000; 75 case QIXIS_SYSCLK_125: 76 return 125000000; 77 case QIXIS_SYSCLK_133: 78 return 133333333; 79 case QIXIS_SYSCLK_150: 80 return 150000000; 81 case QIXIS_SYSCLK_160: 82 return 160000000; 83 case QIXIS_SYSCLK_166: 84 return 166666666; 85 } 86 return 66666666; 87 } 88 89 unsigned long get_board_ddr_clk(void) 90 { 91 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 92 93 switch ((ddrclk_conf & 0x30) >> 4) { 94 case QIXIS_DDRCLK_100: 95 return 100000000; 96 case QIXIS_DDRCLK_125: 97 return 125000000; 98 case QIXIS_DDRCLK_133: 99 return 133333333; 100 } 101 return 66666666; 102 } 103 104 int dram_init(void) 105 { 106 gd->ram_size = initdram(0); 107 108 return 0; 109 } 110 111 #ifdef CONFIG_FSL_ESDHC 112 struct fsl_esdhc_cfg esdhc_cfg[1] = { 113 {CONFIG_SYS_FSL_ESDHC_ADDR}, 114 }; 115 116 int board_mmc_init(bd_t *bis) 117 { 118 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 119 120 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 121 } 122 #endif 123 124 int select_i2c_ch_pca9547(u8 ch) 125 { 126 int ret; 127 128 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 129 if (ret) { 130 puts("PCA: failed to select proper channel\n"); 131 return ret; 132 } 133 134 return 0; 135 } 136 137 int board_early_init_f(void) 138 { 139 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 140 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 141 142 #ifdef CONFIG_TSEC_ENET 143 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 144 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 145 #endif 146 147 #ifdef CONFIG_FSL_IFC 148 init_early_memctl_regs(); 149 #endif 150 151 /* Workaround for the issue that DDR could not respond to 152 * barrier transaction which is generated by executing DSB/ISB 153 * instruction. Set CCI-400 control override register to 154 * terminate the barrier transaction. After DDR is initialized, 155 * allow barrier transaction to DDR again */ 156 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 157 158 return 0; 159 } 160 161 int config_board_mux(int ctrl_type) 162 { 163 u8 reg12; 164 165 reg12 = QIXIS_READ(brdcfg[12]); 166 167 switch (ctrl_type) { 168 case MUX_TYPE_SD_PCI4: 169 reg12 = 0x38; 170 break; 171 case MUX_TYPE_SD_PC_SA_SG_SG: 172 reg12 = 0x01; 173 break; 174 case MUX_TYPE_SD_PC_SA_PC_SG: 175 reg12 = 0x01; 176 break; 177 case MUX_TYPE_SD_PC_SG_SG: 178 reg12 = 0x21; 179 break; 180 default: 181 printf("Wrong mux interface type\n"); 182 return -1; 183 } 184 185 QIXIS_WRITE(brdcfg[12], reg12); 186 187 return 0; 188 } 189 190 int config_serdes_mux(void) 191 { 192 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 193 u32 cfg; 194 195 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 196 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 197 198 switch (cfg) { 199 case 0x0: 200 config_board_mux(MUX_TYPE_SD_PCI4); 201 break; 202 case 0x30: 203 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 204 break; 205 case 0x60: 206 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 207 break; 208 case 0x70: 209 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 210 break; 211 default: 212 printf("SRDS1 prtcl:0x%x\n", cfg); 213 break; 214 } 215 216 return 0; 217 } 218 219 #if defined(CONFIG_MISC_INIT_R) 220 int misc_init_r(void) 221 { 222 #ifdef CONFIG_FSL_CAAM 223 return sec_init(); 224 #endif 225 } 226 #endif 227 228 int board_init(void) 229 { 230 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 231 232 /* Set CCI-400 control override register to 233 * enable barrier transaction */ 234 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 235 /* 236 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register 237 * All transactions are treated as non-shareable 238 */ 239 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 240 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 241 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 242 243 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 244 245 #ifndef CONFIG_SYS_FSL_NO_SERDES 246 fsl_serdes_init(); 247 config_serdes_mux(); 248 #endif 249 250 #ifdef CONFIG_U_QE 251 u_qe_init(); 252 #endif 253 254 return 0; 255 } 256 257 int ft_board_setup(void *blob, bd_t *bd) 258 { 259 ft_cpu_setup(blob, bd); 260 261 return 0; 262 } 263 264 u8 flash_read8(void *addr) 265 { 266 return __raw_readb(addr + 1); 267 } 268 269 void flash_write16(u16 val, void *addr) 270 { 271 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 272 273 __raw_writew(shftval, addr); 274 } 275 276 u16 flash_read16(void *addr) 277 { 278 u16 val = __raw_readw(addr); 279 280 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 281 } 282