1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <mmc.h> 14 #include <fsl_esdhc.h> 15 #include <fsl_ifc.h> 16 17 #include "../common/qixis.h" 18 #include "ls1021aqds_qixis.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 MUX_TYPE_SD_PCI4, 24 MUX_TYPE_SD_PC_SA_SG_SG, 25 MUX_TYPE_SD_PC_SA_PC_SG, 26 MUX_TYPE_SD_PC_SG_SG, 27 }; 28 29 int checkboard(void) 30 { 31 char buf[64]; 32 u8 sw; 33 34 puts("Board: LS1021AQDS\n"); 35 36 sw = QIXIS_READ(brdcfg[0]); 37 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 38 39 if (sw < 0x8) 40 printf("vBank: %d\n", sw); 41 else if (sw == 0x8) 42 puts("PromJet\n"); 43 else if (sw == 0x9) 44 puts("NAND\n"); 45 else if (sw == 0x15) 46 printf("IFCCard\n"); 47 else 48 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 49 50 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 51 QIXIS_READ(id), QIXIS_READ(arch)); 52 53 printf("FPGA: v%d (%s), build %d\n", 54 (int)QIXIS_READ(scver), qixis_read_tag(buf), 55 (int)qixis_read_minor()); 56 57 return 0; 58 } 59 60 unsigned long get_board_sys_clk(void) 61 { 62 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 63 64 switch (sysclk_conf & 0x0f) { 65 case QIXIS_SYSCLK_64: 66 return 64000000; 67 case QIXIS_SYSCLK_83: 68 return 83333333; 69 case QIXIS_SYSCLK_100: 70 return 100000000; 71 case QIXIS_SYSCLK_125: 72 return 125000000; 73 case QIXIS_SYSCLK_133: 74 return 133333333; 75 case QIXIS_SYSCLK_150: 76 return 150000000; 77 case QIXIS_SYSCLK_160: 78 return 160000000; 79 case QIXIS_SYSCLK_166: 80 return 166666666; 81 } 82 return 66666666; 83 } 84 85 unsigned long get_board_ddr_clk(void) 86 { 87 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 88 89 switch ((ddrclk_conf & 0x30) >> 4) { 90 case QIXIS_DDRCLK_100: 91 return 100000000; 92 case QIXIS_DDRCLK_125: 93 return 125000000; 94 case QIXIS_DDRCLK_133: 95 return 133333333; 96 } 97 return 66666666; 98 } 99 100 int dram_init(void) 101 { 102 gd->ram_size = initdram(0); 103 104 return 0; 105 } 106 107 #ifdef CONFIG_FSL_ESDHC 108 struct fsl_esdhc_cfg esdhc_cfg[1] = { 109 {CONFIG_SYS_FSL_ESDHC_ADDR}, 110 }; 111 112 int board_mmc_init(bd_t *bis) 113 { 114 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 115 116 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 117 } 118 #endif 119 120 int select_i2c_ch_pca9547(u8 ch) 121 { 122 int ret; 123 124 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 125 if (ret) { 126 puts("PCA: failed to select proper channel\n"); 127 return ret; 128 } 129 130 return 0; 131 } 132 133 int board_early_init_f(void) 134 { 135 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 136 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 137 138 #ifdef CONFIG_TSEC_ENET 139 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); 140 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 141 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); 142 #endif 143 144 #ifdef CONFIG_FSL_IFC 145 init_early_memctl_regs(); 146 #endif 147 148 /* Workaround for the issue that DDR could not respond to 149 * barrier transaction which is generated by executing DSB/ISB 150 * instruction. Set CCI-400 control override register to 151 * terminate the barrier transaction. After DDR is initialized, 152 * allow barrier transaction to DDR again */ 153 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 154 155 return 0; 156 } 157 158 int config_board_mux(int ctrl_type) 159 { 160 u8 reg12; 161 162 reg12 = QIXIS_READ(brdcfg[12]); 163 164 switch (ctrl_type) { 165 case MUX_TYPE_SD_PCI4: 166 reg12 = 0x38; 167 break; 168 case MUX_TYPE_SD_PC_SA_SG_SG: 169 reg12 = 0x01; 170 break; 171 case MUX_TYPE_SD_PC_SA_PC_SG: 172 reg12 = 0x01; 173 break; 174 case MUX_TYPE_SD_PC_SG_SG: 175 reg12 = 0x21; 176 break; 177 default: 178 printf("Wrong mux interface type\n"); 179 return -1; 180 } 181 182 QIXIS_WRITE(brdcfg[12], reg12); 183 184 return 0; 185 } 186 187 int config_serdes_mux(void) 188 { 189 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 190 u32 cfg; 191 192 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 193 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 194 195 switch (cfg) { 196 case 0x0: 197 config_board_mux(MUX_TYPE_SD_PCI4); 198 break; 199 case 0x30: 200 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 201 break; 202 case 0x60: 203 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 204 break; 205 case 0x70: 206 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 207 break; 208 default: 209 printf("SRDS1 prtcl:0x%x\n", cfg); 210 break; 211 } 212 213 return 0; 214 } 215 216 int board_init(void) 217 { 218 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 219 220 /* Set CCI-400 control override register to 221 * enable barrier transaction */ 222 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 223 224 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 225 226 #ifndef CONFIG_SYS_FSL_NO_SERDES 227 fsl_serdes_init(); 228 config_serdes_mux(); 229 #endif 230 return 0; 231 } 232 233 void ft_board_setup(void *blob, bd_t *bd) 234 { 235 ft_cpu_setup(blob, bd); 236 } 237 238 u8 flash_read8(void *addr) 239 { 240 return __raw_readb(addr + 1); 241 } 242 243 void flash_write16(u16 val, void *addr) 244 { 245 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 246 247 __raw_writew(shftval, addr); 248 } 249 250 u16 flash_read16(void *addr) 251 { 252 u16 val = __raw_readw(addr); 253 254 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 255 } 256