1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __DDR_H__
8 #define __DDR_H__
9 struct board_specific_parameters {
10 	u32 n_ranks;
11 	u32 datarate_mhz_high;
12 	u32 rank_gb;
13 	u32 clk_adjust;
14 	u32 wrlvl_start;
15 	u32 wrlvl_ctl_2;
16 	u32 wrlvl_ctl_3;
17 	u32 cpo_override;
18 	u32 write_data_delay;
19 	u32 force_2t;
20 };
21 
22 /*
23  * These tables contain all valid speeds we want to override with board
24  * specific parameters. datarate_mhz_high values need to be in ascending order
25  * for each n_ranks group.
26  */
27 static const struct board_specific_parameters udimm0[] = {
28 	/*
29 	 * memory controller 0
30 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
31 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
32 	 */
33 #ifdef CONFIG_SYS_FSL_DDR4
34 	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
35 	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
36 	{1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
37 	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
38 	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
39 #elif defined(CONFIG_SYS_FSL_DDR3)
40 	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
41 	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
42 	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
43 	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
44 	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
45 	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
46 	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
47 	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
48 	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
49 #else
50 #error DDR type not defined
51 #endif
52 	{}
53 };
54 
55 static const struct board_specific_parameters *udimms[] = {
56 	udimm0,
57 };
58 
59 #endif
60