1550e3dc0SWang Huan /* 2550e3dc0SWang Huan * Copyright 2014 Freescale Semiconductor, Inc. 3550e3dc0SWang Huan * 4550e3dc0SWang Huan * SPDX-License-Identifier: GPL-2.0+ 5550e3dc0SWang Huan */ 6550e3dc0SWang Huan 7550e3dc0SWang Huan #ifndef __DDR_H__ 8550e3dc0SWang Huan #define __DDR_H__ 9550e3dc0SWang Huan struct board_specific_parameters { 10550e3dc0SWang Huan u32 n_ranks; 11550e3dc0SWang Huan u32 datarate_mhz_high; 12550e3dc0SWang Huan u32 rank_gb; 13550e3dc0SWang Huan u32 clk_adjust; 14550e3dc0SWang Huan u32 wrlvl_start; 15550e3dc0SWang Huan u32 wrlvl_ctl_2; 16550e3dc0SWang Huan u32 wrlvl_ctl_3; 17550e3dc0SWang Huan u32 cpo_override; 18550e3dc0SWang Huan u32 write_data_delay; 19550e3dc0SWang Huan u32 force_2t; 20550e3dc0SWang Huan }; 21550e3dc0SWang Huan 22550e3dc0SWang Huan /* 23550e3dc0SWang Huan * These tables contain all valid speeds we want to override with board 24550e3dc0SWang Huan * specific parameters. datarate_mhz_high values need to be in ascending order 25550e3dc0SWang Huan * for each n_ranks group. 26550e3dc0SWang Huan */ 27550e3dc0SWang Huan static const struct board_specific_parameters udimm0[] = { 28550e3dc0SWang Huan /* 29550e3dc0SWang Huan * memory controller 0 30550e3dc0SWang Huan * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 31550e3dc0SWang Huan * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 32550e3dc0SWang Huan */ 33*c7eae7fcSYork Sun #ifdef CONFIG_SYS_FSL_DDR4 34*c7eae7fcSYork Sun {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, 35*c7eae7fcSYork Sun {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, 36*c7eae7fcSYork Sun {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, 37*c7eae7fcSYork Sun {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, 38*c7eae7fcSYork Sun {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, 39*c7eae7fcSYork Sun #elif defined(CONFIG_SYS_FSL_DDR3) 40550e3dc0SWang Huan {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 41550e3dc0SWang Huan {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 42550e3dc0SWang Huan {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 43550e3dc0SWang Huan {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 44550e3dc0SWang Huan {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 45550e3dc0SWang Huan {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 46550e3dc0SWang Huan {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 47550e3dc0SWang Huan {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 48550e3dc0SWang Huan {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 49*c7eae7fcSYork Sun #else 50*c7eae7fcSYork Sun #error DDR type not defined 51*c7eae7fcSYork Sun #endif 52550e3dc0SWang Huan {} 53550e3dc0SWang Huan }; 54550e3dc0SWang Huan 55550e3dc0SWang Huan static const struct board_specific_parameters *udimms[] = { 56550e3dc0SWang Huan udimm0, 57550e3dc0SWang Huan }; 58550e3dc0SWang Huan 59550e3dc0SWang Huan #endif 60