1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <fsl_ddr_sdram.h> 8 #include <fsl_ddr_dimm_params.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include "ddr.h" 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 void fsl_ddr_board_options(memctl_options_t *popts, 16 dimm_params_t *pdimm, 17 unsigned int ctrl_num) 18 { 19 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 20 ulong ddr_freq; 21 22 if (ctrl_num > 3) { 23 printf("Not supported controller number %d\n", ctrl_num); 24 return; 25 } 26 if (!pdimm->n_ranks) 27 return; 28 29 pbsp = udimms[0]; 30 31 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 32 * freqency and n_banks specified in board_specific_parameters table. 33 */ 34 ddr_freq = get_ddr_freq(0) / 1000000; 35 while (pbsp->datarate_mhz_high) { 36 if (pbsp->n_ranks == pdimm->n_ranks) { 37 if (ddr_freq <= pbsp->datarate_mhz_high) { 38 popts->clk_adjust = pbsp->clk_adjust; 39 popts->wrlvl_start = pbsp->wrlvl_start; 40 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 41 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 42 popts->cpo_override = pbsp->cpo_override; 43 popts->write_data_delay = 44 pbsp->write_data_delay; 45 goto found; 46 } 47 pbsp_highest = pbsp; 48 } 49 pbsp++; 50 } 51 52 if (pbsp_highest) { 53 printf("Error: board specific timing not found for %lu MT/s\n", 54 ddr_freq); 55 printf("Trying to use the highest speed (%u) parameters\n", 56 pbsp_highest->datarate_mhz_high); 57 popts->clk_adjust = pbsp_highest->clk_adjust; 58 popts->wrlvl_start = pbsp_highest->wrlvl_start; 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 61 } else { 62 panic("DIMM is not supported by this board"); 63 } 64 found: 65 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 66 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 67 68 /* force DDR bus width to 32 bits */ 69 popts->data_bus_width = 1; 70 popts->otf_burst_chop_en = 0; 71 popts->burst_length = DDR_BL8; 72 73 /* 74 * Factors to consider for half-strength driver enable: 75 * - number of DIMMs installed 76 */ 77 popts->half_strength_driver_enable = 1; 78 /* 79 * Write leveling override 80 */ 81 popts->wrlvl_override = 1; 82 popts->wrlvl_sample = 0xf; 83 84 /* 85 * Rtt and Rtt_WR override 86 */ 87 popts->rtt_override = 0; 88 89 /* Enable ZQ calibration */ 90 popts->zq_en = 1; 91 92 #ifdef CONFIG_SYS_FSL_DDR4 93 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 94 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 95 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 96 #else 97 popts->cswl_override = DDR_CSWL_CS0; 98 99 /* optimize cpo for erratum A-009942 */ 100 popts->cpo_sample = 0x58; 101 102 /* DHC_EN =1, ODT = 75 Ohm */ 103 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 104 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 105 #endif 106 } 107 108 #ifdef CONFIG_SYS_DDR_RAW_TIMING 109 dimm_params_t ddr_raw_timing = { 110 .n_ranks = 1, 111 .rank_density = 1073741824u, 112 .capacity = 1073741824u, 113 .primary_sdram_width = 32, 114 .ec_sdram_width = 0, 115 .registered_dimm = 0, 116 .mirrored_dimm = 0, 117 .n_row_addr = 15, 118 .n_col_addr = 10, 119 .n_banks_per_sdram_device = 8, 120 .edc_config = 0, 121 .burst_lengths_bitmask = 0x0c, 122 123 .tckmin_x_ps = 1071, 124 .caslat_x = 0xfe << 4, /* 5,6,7,8 */ 125 .taa_ps = 13125, 126 .twr_ps = 15000, 127 .trcd_ps = 13125, 128 .trrd_ps = 7500, 129 .trp_ps = 13125, 130 .tras_ps = 37500, 131 .trc_ps = 50625, 132 .trfc_ps = 160000, 133 .twtr_ps = 7500, 134 .trtp_ps = 7500, 135 .refresh_rate_ps = 7800000, 136 .tfaw_ps = 37500, 137 }; 138 139 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 140 unsigned int controller_number, 141 unsigned int dimm_number) 142 { 143 static const char dimm_model[] = "Fixed DDR on board"; 144 145 if (((controller_number == 0) && (dimm_number == 0)) || 146 ((controller_number == 1) && (dimm_number == 0))) { 147 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 148 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 149 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 150 } 151 152 return 0; 153 } 154 #endif 155 156 #if defined(CONFIG_DEEP_SLEEP) 157 void board_mem_sleep_setup(void) 158 { 159 void __iomem *qixis_base = (void *)QIXIS_BASE; 160 161 /* does not provide HW signals for power management */ 162 clrbits_8(qixis_base + 0x21, 0x2); 163 udelay(1); 164 } 165 #endif 166 167 int fsl_initdram(void) 168 { 169 phys_size_t dram_size; 170 171 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) 172 puts("Initializing DDR....using SPD\n"); 173 dram_size = fsl_ddr_sdram(); 174 #else 175 dram_size = fsl_ddr_sdram_size(); 176 #endif 177 178 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 179 fsl_dp_resume(); 180 #endif 181 182 erratum_a008850_post(); 183 184 gd->ram_size = dram_size; 185 186 return 0; 187 } 188 189 int dram_init_banksize(void) 190 { 191 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 192 gd->bd->bi_dram[0].size = gd->ram_size; 193 194 return 0; 195 } 196