1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <fsl_ddr_dimm_params.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include "ddr.h" 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 void fsl_ddr_board_options(memctl_options_t *popts, 17 dimm_params_t *pdimm, 18 unsigned int ctrl_num) 19 { 20 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 21 ulong ddr_freq; 22 23 if (ctrl_num > 3) { 24 printf("Not supported controller number %d\n", ctrl_num); 25 return; 26 } 27 if (!pdimm->n_ranks) 28 return; 29 30 pbsp = udimms[0]; 31 32 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 33 * freqency and n_banks specified in board_specific_parameters table. 34 */ 35 ddr_freq = get_ddr_freq(0) / 1000000; 36 while (pbsp->datarate_mhz_high) { 37 if (pbsp->n_ranks == pdimm->n_ranks) { 38 if (ddr_freq <= pbsp->datarate_mhz_high) { 39 popts->clk_adjust = pbsp->clk_adjust; 40 popts->wrlvl_start = pbsp->wrlvl_start; 41 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 42 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 43 popts->cpo_override = pbsp->cpo_override; 44 popts->write_data_delay = 45 pbsp->write_data_delay; 46 goto found; 47 } 48 pbsp_highest = pbsp; 49 } 50 pbsp++; 51 } 52 53 if (pbsp_highest) { 54 printf("Error: board specific timing not found for %lu MT/s\n", 55 ddr_freq); 56 printf("Trying to use the highest speed (%u) parameters\n", 57 pbsp_highest->datarate_mhz_high); 58 popts->clk_adjust = pbsp_highest->clk_adjust; 59 popts->wrlvl_start = pbsp_highest->wrlvl_start; 60 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 61 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 62 } else { 63 panic("DIMM is not supported by this board"); 64 } 65 found: 66 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 67 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 68 69 /* force DDR bus width to 32 bits */ 70 popts->data_bus_width = 1; 71 popts->otf_burst_chop_en = 0; 72 popts->burst_length = DDR_BL8; 73 74 /* 75 * Factors to consider for half-strength driver enable: 76 * - number of DIMMs installed 77 */ 78 popts->half_strength_driver_enable = 1; 79 /* 80 * Write leveling override 81 */ 82 popts->wrlvl_override = 1; 83 popts->wrlvl_sample = 0xf; 84 85 /* 86 * Rtt and Rtt_WR override 87 */ 88 popts->rtt_override = 0; 89 90 /* Enable ZQ calibration */ 91 popts->zq_en = 1; 92 93 #ifdef CONFIG_SYS_FSL_DDR4 94 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 95 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 96 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 97 #else 98 popts->cswl_override = DDR_CSWL_CS0; 99 100 /* optimize cpo for erratum A-009942 */ 101 popts->cpo_sample = 0x58; 102 103 /* DHC_EN =1, ODT = 75 Ohm */ 104 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 105 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 106 #endif 107 } 108 109 #ifdef CONFIG_SYS_DDR_RAW_TIMING 110 dimm_params_t ddr_raw_timing = { 111 .n_ranks = 1, 112 .rank_density = 1073741824u, 113 .capacity = 1073741824u, 114 .primary_sdram_width = 32, 115 .ec_sdram_width = 0, 116 .registered_dimm = 0, 117 .mirrored_dimm = 0, 118 .n_row_addr = 15, 119 .n_col_addr = 10, 120 .n_banks_per_sdram_device = 8, 121 .edc_config = 0, 122 .burst_lengths_bitmask = 0x0c, 123 124 .tckmin_x_ps = 1071, 125 .caslat_x = 0xfe << 4, /* 5,6,7,8 */ 126 .taa_ps = 13125, 127 .twr_ps = 15000, 128 .trcd_ps = 13125, 129 .trrd_ps = 7500, 130 .trp_ps = 13125, 131 .tras_ps = 37500, 132 .trc_ps = 50625, 133 .trfc_ps = 160000, 134 .twtr_ps = 7500, 135 .trtp_ps = 7500, 136 .refresh_rate_ps = 7800000, 137 .tfaw_ps = 37500, 138 }; 139 140 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 141 unsigned int controller_number, 142 unsigned int dimm_number) 143 { 144 static const char dimm_model[] = "Fixed DDR on board"; 145 146 if (((controller_number == 0) && (dimm_number == 0)) || 147 ((controller_number == 1) && (dimm_number == 0))) { 148 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 149 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 150 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 151 } 152 153 return 0; 154 } 155 #endif 156 157 #if defined(CONFIG_DEEP_SLEEP) 158 void board_mem_sleep_setup(void) 159 { 160 void __iomem *qixis_base = (void *)QIXIS_BASE; 161 162 /* does not provide HW signals for power management */ 163 clrbits_8(qixis_base + 0x21, 0x2); 164 udelay(1); 165 } 166 #endif 167 168 int fsl_initdram(void) 169 { 170 phys_size_t dram_size; 171 172 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) 173 puts("Initializing DDR....using SPD\n"); 174 dram_size = fsl_ddr_sdram(); 175 #else 176 dram_size = fsl_ddr_sdram_size(); 177 #endif 178 179 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) 180 fsl_dp_resume(); 181 #endif 182 183 gd->ram_size = dram_size; 184 185 return 0; 186 } 187 188 int dram_init_banksize(void) 189 { 190 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 191 gd->bd->bi_dram[0].size = gd->ram_size; 192 193 return 0; 194 } 195