1550e3dc0SWang HuanOverview 2550e3dc0SWang Huan-------- 3550e3dc0SWang HuanThe LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. 4550e3dc0SWang Huan 5550e3dc0SWang HuanLS1021A SoC Overview 6550e3dc0SWang Huan------------------ 7550e3dc0SWang HuanThe QorIQ LS1 family, which includes the LS1021A communications processor, 8550e3dc0SWang Huanis built on Layerscape architecture, the industry's first software-aware, 9550e3dc0SWang Huancore-agnostic networking architecture to offer unprecedented efficiency 10550e3dc0SWang Huanand scale. 11550e3dc0SWang Huan 12550e3dc0SWang HuanA member of the value-performance tier, the QorIQ LS1021A processor provides 13550e3dc0SWang Huanextensive integration and power efficiency for fanless, small form factor 14550e3dc0SWang Huanenterprise networking applications. Incorporating dual ARM Cortex-A7 cores 15550e3dc0SWang Huanrunning up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark 16550e3dc0SWang Huanperformance of over 6,000, as well as virtualization support, advanced 17550e3dc0SWang Huansecurity features and the broadest array of high-speed interconnects and 18550e3dc0SWang Huanoptimized peripheral features ever offered in a sub-3 W processor. 19550e3dc0SWang Huan 20550e3dc0SWang HuanThe QorIQ LS1021A processor features an integrated LCD controller, 21550e3dc0SWang HuanCAN controller for implementing industrial protocols, DDR3L/4 running 22550e3dc0SWang Huanup to 1600 MHz, integrated security engine and QUICC Engine, and ECC 23550e3dc0SWang Huanprotection on both L1 and L2 caches. The LS1021A processor is pin- and 24550e3dc0SWang Huansoftware-compatible with the QorIQ LS1020A and LS1022A processors. 25550e3dc0SWang Huan 26550e3dc0SWang HuanThe LS1021A SoC includes the following function and features: 27550e3dc0SWang Huan 28550e3dc0SWang Huan - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture 29550e3dc0SWang Huan - Dual high-preformance ARM Cortex-A7 cores, each core includes: 30550e3dc0SWang Huan - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) 31550e3dc0SWang Huan - 512 Kbyte shared coherent L2 Cache (with ECC protection) 32550e3dc0SWang Huan - NEON Co-processor (per core) 33550e3dc0SWang Huan - 40-bit physical addressing 34550e3dc0SWang Huan - Vector floating-point support 35550e3dc0SWang Huan - ARM Core-Link CCI-400 Cache Coherent Interconnect 36550e3dc0SWang Huan - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration 37550e3dc0SWang Huan supporting speeds up to 1600Mtps 38550e3dc0SWang Huan - ECC and interleaving support 39550e3dc0SWang Huan - VeTSEC Ethernet complex 40550e3dc0SWang Huan - Up to 3x virtualized 10/100/1000 Ethernet controllers 41550e3dc0SWang Huan - MII, RMII, RGMII, and SGMII support 42550e3dc0SWang Huan - QoS, lossless flow control, and IEEE 1588 support 43550e3dc0SWang Huan - 4-lane 6GHz SerDes 44550e3dc0SWang Huan - High speed interconnect (4 SerDes lanes with are muxed for these protocol) 45550e3dc0SWang Huan - Two PCI Express Gen2 controllers running at up to 5 GHz 46550e3dc0SWang Huan - One Serial ATA 3.0 supporting 6 GT/s operation 47550e3dc0SWang Huan - Two SGMII interfaces supporting 1000 Mbps 48550e3dc0SWang Huan - Additional peripheral interfaces 49550e3dc0SWang Huan - One high-speed USB 3.0 controller with integrated PHY and one high-speed 50550e3dc0SWang Huan USB 2.00 controller with ULPI 51550e3dc0SWang Huan - Integrated flash controller (IFC) with 16-bit interface 52550e3dc0SWang Huan - Quad SPI NOR Flash 53550e3dc0SWang Huan - One enhanced Secure digital host controller 54550e3dc0SWang Huan - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) 55550e3dc0SWang Huan - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power 56550e3dc0SWang Huan UARTs 57550e3dc0SWang Huan - Three I2C controllers 58550e3dc0SWang Huan - Eight FlexTimers four supporting PWM and four FlexCAN ports 59550e3dc0SWang Huan - Four GPIO controllers supporting up to 109 general purpose I/O signals 60550e3dc0SWang Huan - Integrated advanced audio block: 61550e3dc0SWang Huan - Four synchronous audio interfaces (SAI) 62550e3dc0SWang Huan - Sony/Philips Digital Interconnect Format (SPDIF) 63550e3dc0SWang Huan - Asynchronous Sample Rate Converter (ASRC) 64550e3dc0SWang Huan - Hardware based crypto offload engine 65550e3dc0SWang Huan - IPSec forwarding at up to 1Gbps 66550e3dc0SWang Huan - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported 67550e3dc0SWang Huan - Public key hardware accelerator 68550e3dc0SWang Huan - True Random Number Generator (NIST Certified) 69550e3dc0SWang Huan - Advanced Encryption Standard Accelerators (AESA) 70550e3dc0SWang Huan - Data Encryption Standard Accelerators 71550e3dc0SWang Huan - QUICC Engine ULite block 72550e3dc0SWang Huan - Two universal communication controllers (TDM and HDLC) supporting 64 73550e3dc0SWang Huan multichannels, each running at 64 Kbps 74550e3dc0SWang Huan - Support for 256 channels of HDLC 75550e3dc0SWang Huan - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported 76550e3dc0SWang Huan 77550e3dc0SWang HuanLS1021AQDS board Overview 78550e3dc0SWang Huan------------------------- 79550e3dc0SWang Huan - DDR Controller 80550e3dc0SWang Huan - Supports rates of up to 1600 MHz data-rate 81550e3dc0SWang Huan - Supports one DDR3LP UDIMM, of single-, dual- types. 82550e3dc0SWang Huan - IFC/Local Bus 83550e3dc0SWang Huan - NAND flash: 512M 8-bit NAND flash 84550e3dc0SWang Huan - NOR: 128MB 16-bit NOR Flash 85550e3dc0SWang Huan - Ethernet 86550e3dc0SWang Huan - Three on-board RGMII 10/100/1G ethernet ports. 87550e3dc0SWang Huan - FPGA 88550e3dc0SWang Huan - Clocks 89550e3dc0SWang Huan - System and DDR clock (SYSCLK, DDRCLK) 90550e3dc0SWang Huan - SERDES clocks 91550e3dc0SWang Huan - Power Supplies 92550e3dc0SWang Huan - SDHC 93550e3dc0SWang Huan - SDHC/SDXC connector 94550e3dc0SWang Huan - Other IO 95550e3dc0SWang Huan - Two Serial ports 96550e3dc0SWang Huan - Three I2C ports 97550e3dc0SWang Huan 98550e3dc0SWang HuanMemory map 99550e3dc0SWang Huan----------- 100550e3dc0SWang HuanThe addresses in brackets are physical addresses. 101550e3dc0SWang Huan 102550e3dc0SWang HuanStart Address End Address Description Size 103550e3dc0SWang Huan0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 104550e3dc0SWang Huan0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 105550e3dc0SWang Huan0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 106550e3dc0SWang Huan0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 107550e3dc0SWang Huan0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 108550e3dc0SWang Huan0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB 109550e3dc0SWang Huan0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 110550e3dc0SWang Huan0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 111550e3dc0SWang Huan0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 112550e3dc0SWang Huan0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB 113*f85a8e8dSXiaoliang Yang 114*f85a8e8dSXiaoliang YangLS1021a rev1.0 Soc specific Options/Settings 115*f85a8e8dSXiaoliang Yang-------------------------------------------- 116*f85a8e8dSXiaoliang YangIf the LS1021a Soc is rev1.0, you need modify the configure file. 117*f85a8e8dSXiaoliang YangAdd the following define in include/configs/ls1021aqds.h: 118*f85a8e8dSXiaoliang Yang#define CONFIG_SKIP_LOWLEVEL_INIT 119