1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/immap_ls102xa.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <asm/arch/ls102xa_stream_id.h> 12 13 #include <asm/arch/ls102xa_devdis.h> 14 #include <asm/arch/ls102xa_soc.h> 15 #include <asm/arch/ls102xa_sata.h> 16 #include <fsl_csu.h> 17 #include <fsl_esdhc.h> 18 #include <fsl_immap.h> 19 #include <netdev.h> 20 #include <fsl_mdio.h> 21 #include <tsec.h> 22 #include <spl.h> 23 24 #include <fsl_validate.h> 25 #include "../common/sleep.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define DDR_SIZE 0x40000000 30 31 32 int checkboard(void) 33 { 34 puts("Board: LS1021AIOT\n"); 35 36 #ifndef CONFIG_QSPI_BOOT 37 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 38 u32 cpldrev; 39 40 cpldrev = in_be32(&dcfg->gpporcr1); 41 42 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & 43 0xf)); 44 #endif 45 return 0; 46 } 47 48 void ddrmc_init(void) 49 { 50 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 51 u32 temp_sdram_cfg, tmp; 52 53 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 54 55 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 56 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 57 58 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 59 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 60 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 61 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 62 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 63 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 64 65 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 66 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 67 68 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 69 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 70 71 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 72 73 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 74 75 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 76 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 77 78 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 79 80 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 81 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 82 83 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 84 85 /* DDR erratum A-009942 */ 86 tmp = in_be32(&ddr->debug[28]); 87 out_be32(&ddr->debug[28], tmp | 0x0070006f); 88 89 udelay(500); 90 91 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 92 93 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 94 } 95 96 int dram_init(void) 97 { 98 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 99 ddrmc_init(); 100 #endif 101 102 gd->ram_size = DDR_SIZE; 103 return 0; 104 } 105 106 #ifdef CONFIG_FSL_ESDHC 107 struct fsl_esdhc_cfg esdhc_cfg[1] = { 108 {CONFIG_SYS_FSL_ESDHC_ADDR}, 109 }; 110 111 int board_mmc_init(bd_t *bis) 112 { 113 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 114 115 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 116 } 117 118 #endif 119 120 #ifdef CONFIG_TSEC_ENET 121 int board_eth_init(bd_t *bis) 122 { 123 struct fsl_pq_mdio_info mdio_info; 124 struct tsec_info_struct tsec_info[4]; 125 int num = 0; 126 127 #ifdef CONFIG_TSEC1 128 SET_STD_TSEC_INFO(tsec_info[num], 1); 129 if (is_serdes_configured(SGMII_TSEC1)) { 130 puts("eTSEC1 is in sgmii mode.\n"); 131 tsec_info[num].flags |= TSEC_SGMII; 132 } 133 num++; 134 #endif 135 #ifdef CONFIG_TSEC2 136 SET_STD_TSEC_INFO(tsec_info[num], 2); 137 if (is_serdes_configured(SGMII_TSEC2)) { 138 puts("eTSEC2 is in sgmii mode.\n"); 139 tsec_info[num].flags |= TSEC_SGMII; 140 } 141 num++; 142 #endif 143 if (!num) { 144 printf("No TSECs initialized\n"); 145 return 0; 146 } 147 148 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 149 mdio_info.name = DEFAULT_MII_NAME; 150 fsl_pq_mdio_init(bis, &mdio_info); 151 152 tsec_eth_init(bis, tsec_info, num); 153 154 return pci_eth_init(bis); 155 } 156 #endif 157 158 int board_early_init_f(void) 159 { 160 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 161 162 #ifdef CONFIG_TSEC_ENET 163 /* clear BD & FR bits for BE BD's and frame data */ 164 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 165 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 166 167 #endif 168 169 arch_soc_init(); 170 171 return 0; 172 } 173 174 #ifdef CONFIG_SPL_BUILD 175 void board_init_f(ulong dummy) 176 { 177 /* Clear the BSS */ 178 memset(__bss_start, 0, __bss_end - __bss_start); 179 180 get_clocks(); 181 182 preloader_console_init(); 183 184 dram_init(); 185 186 /* Allow OCRAM access permission as R/W */ 187 188 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 189 enable_layerscape_ns_access(); 190 #endif 191 192 board_init_r(NULL, 0); 193 } 194 #endif 195 196 int board_init(void) 197 { 198 #ifndef CONFIG_SYS_FSL_NO_SERDES 199 fsl_serdes_init(); 200 #endif 201 202 ls102xa_smmu_stream_id_init(); 203 204 return 0; 205 } 206 207 #ifdef CONFIG_BOARD_LATE_INIT 208 int board_late_init(void) 209 { 210 #ifdef CONFIG_SCSI_AHCI_PLAT 211 ls1021a_sata_init(); 212 #endif 213 214 return 0; 215 } 216 #endif 217 218 #if defined(CONFIG_MISC_INIT_R) 219 int misc_init_r(void) 220 { 221 #ifdef CONFIG_FSL_DEVICE_DISABLE 222 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 223 224 #endif 225 226 #ifdef CONFIG_FSL_CAAM 227 return sec_init(); 228 #endif 229 } 230 #endif 231 232 int ft_board_setup(void *blob, bd_t *bd) 233 { 234 ft_cpu_setup(blob, bd); 235 236 #ifdef CONFIG_PCI 237 ft_pci_setup(blob, bd); 238 #endif 239 240 return 0; 241 } 242 243 void flash_write16(u16 val, void *addr) 244 { 245 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 246 247 __raw_writew(shftval, addr); 248 } 249 250 u16 flash_read16(void *addr) 251 { 252 u16 val = __raw_readw(addr); 253 254 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 255 } 256