1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/arch/immap_ls102xa.h> 8 #include <asm/arch/clock.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <asm/arch/ls102xa_stream_id.h> 11 12 #include <asm/arch/ls102xa_devdis.h> 13 #include <asm/arch/ls102xa_soc.h> 14 #include <fsl_csu.h> 15 #include <fsl_esdhc.h> 16 #include <fsl_immap.h> 17 #include <netdev.h> 18 #include <fsl_mdio.h> 19 #include <tsec.h> 20 #include <spl.h> 21 22 #include <fsl_validate.h> 23 #include "../common/sleep.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define DDR_SIZE 0x40000000 28 29 30 int checkboard(void) 31 { 32 puts("Board: LS1021AIOT\n"); 33 34 #ifndef CONFIG_QSPI_BOOT 35 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 36 u32 cpldrev; 37 38 cpldrev = in_be32(&dcfg->gpporcr1); 39 40 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & 41 0xf)); 42 #endif 43 return 0; 44 } 45 46 void ddrmc_init(void) 47 { 48 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; 49 u32 temp_sdram_cfg, tmp; 50 51 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); 52 53 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); 54 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); 55 56 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); 57 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); 58 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); 59 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); 60 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); 61 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); 62 63 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); 64 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); 65 66 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); 67 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); 68 69 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); 70 71 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); 72 73 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); 74 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); 75 76 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); 77 78 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); 79 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); 80 81 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); 82 83 /* DDR erratum A-009942 */ 84 tmp = in_be32(&ddr->debug[28]); 85 out_be32(&ddr->debug[28], tmp | 0x0070006f); 86 87 udelay(500); 88 89 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); 90 91 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); 92 } 93 94 int dram_init(void) 95 { 96 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 97 ddrmc_init(); 98 #endif 99 100 gd->ram_size = DDR_SIZE; 101 return 0; 102 } 103 104 #ifdef CONFIG_FSL_ESDHC 105 struct fsl_esdhc_cfg esdhc_cfg[1] = { 106 {CONFIG_SYS_FSL_ESDHC_ADDR}, 107 }; 108 109 int board_mmc_init(bd_t *bis) 110 { 111 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 112 113 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 114 } 115 116 #endif 117 118 #ifdef CONFIG_TSEC_ENET 119 int board_eth_init(bd_t *bis) 120 { 121 struct fsl_pq_mdio_info mdio_info; 122 struct tsec_info_struct tsec_info[4]; 123 int num = 0; 124 125 #ifdef CONFIG_TSEC1 126 SET_STD_TSEC_INFO(tsec_info[num], 1); 127 if (is_serdes_configured(SGMII_TSEC1)) { 128 puts("eTSEC1 is in sgmii mode.\n"); 129 tsec_info[num].flags |= TSEC_SGMII; 130 } 131 num++; 132 #endif 133 #ifdef CONFIG_TSEC2 134 SET_STD_TSEC_INFO(tsec_info[num], 2); 135 if (is_serdes_configured(SGMII_TSEC2)) { 136 puts("eTSEC2 is in sgmii mode.\n"); 137 tsec_info[num].flags |= TSEC_SGMII; 138 } 139 num++; 140 #endif 141 if (!num) { 142 printf("No TSECs initialized\n"); 143 return 0; 144 } 145 146 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 147 mdio_info.name = DEFAULT_MII_NAME; 148 fsl_pq_mdio_init(bis, &mdio_info); 149 150 tsec_eth_init(bis, tsec_info, num); 151 152 return pci_eth_init(bis); 153 } 154 #endif 155 156 int board_early_init_f(void) 157 { 158 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 159 160 #ifdef CONFIG_TSEC_ENET 161 /* clear BD & FR bits for BE BD's and frame data */ 162 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 163 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 164 165 #endif 166 167 arch_soc_init(); 168 169 return 0; 170 } 171 172 #ifdef CONFIG_SPL_BUILD 173 void board_init_f(ulong dummy) 174 { 175 /* Clear the BSS */ 176 memset(__bss_start, 0, __bss_end - __bss_start); 177 178 get_clocks(); 179 180 preloader_console_init(); 181 182 dram_init(); 183 184 /* Allow OCRAM access permission as R/W */ 185 186 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 187 enable_layerscape_ns_access(); 188 #endif 189 190 board_init_r(NULL, 0); 191 } 192 #endif 193 194 int board_init(void) 195 { 196 #ifndef CONFIG_SYS_FSL_NO_SERDES 197 fsl_serdes_init(); 198 #endif 199 200 ls102xa_smmu_stream_id_init(); 201 202 return 0; 203 } 204 205 #ifdef CONFIG_BOARD_LATE_INIT 206 int board_late_init(void) 207 { 208 return 0; 209 } 210 #endif 211 212 #if defined(CONFIG_MISC_INIT_R) 213 int misc_init_r(void) 214 { 215 #ifdef CONFIG_FSL_DEVICE_DISABLE 216 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); 217 218 #endif 219 220 #ifdef CONFIG_FSL_CAAM 221 return sec_init(); 222 #endif 223 } 224 #endif 225 226 int ft_board_setup(void *blob, bd_t *bd) 227 { 228 ft_cpu_setup(blob, bd); 229 230 #ifdef CONFIG_PCI 231 ft_pci_setup(blob, bd); 232 #endif 233 234 return 0; 235 } 236 237 void flash_write16(u16 val, void *addr) 238 { 239 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 240 241 __raw_writew(shftval, addr); 242 } 243 244 u16 flash_read16(void *addr) 245 { 246 u16 val = __raw_readw(addr); 247 248 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 249 } 250