1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #ifdef CONFIG_FSL_LS_PPA
12 #include <asm/arch/ppa.h>
13 #endif
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/soc.h>
16 #include <hwconfig.h>
17 #include <ahci.h>
18 #include <mmc.h>
19 #include <scsi.h>
20 #include <fsl_esdhc.h>
21 #include <environment.h>
22 #include <fsl_mmdc.h>
23 #include <netdev.h>
24 #include <fsl_sec.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 #define BOOT_FROM_UPPER_BANK	0x2
29 #define BOOT_FROM_LOWER_BANK	0x1
30 
31 int checkboard(void)
32 {
33 #ifdef CONFIG_TARGET_LS1012ARDB
34 	u8 in1;
35 
36 	puts("Board: LS1012ARDB ");
37 
38 	/* Initialize i2c early for Serial flash bank information */
39 	i2c_set_bus_num(0);
40 
41 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
42 		printf("Error reading i2c boot information!\n");
43 		return 0; /* Don't want to hang() on this error */
44 	}
45 
46 	puts("Version");
47 	switch (in1 & SW_REV_MASK) {
48 	case SW_REV_A:
49 		puts(": RevA");
50 		break;
51 	case SW_REV_B:
52 		puts(": RevB");
53 		break;
54 	case SW_REV_C:
55 		puts(": RevC");
56 		break;
57 	case SW_REV_C1:
58 		puts(": RevC1");
59 		break;
60 	case SW_REV_C2:
61 		puts(": RevC2");
62 		break;
63 	case SW_REV_D:
64 		puts(": RevD");
65 		break;
66 	case SW_REV_E:
67 		puts(": RevE");
68 		break;
69 	default:
70 		puts(": unknown");
71 		break;
72 	}
73 
74 	printf(", boot from QSPI");
75 	if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
76 		puts(": emu\n");
77 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
78 		puts(": bank1\n");
79 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
80 		puts(": bank2\n");
81 	else
82 		puts("unknown\n");
83 #else
84 
85 	puts("Board: LS1012A2G5RDB ");
86 #endif
87 	return 0;
88 }
89 
90 int dram_init(void)
91 {
92 	static const struct fsl_mmdc_info mparam = {
93 		0x05180000,	/* mdctl */
94 		0x00030035,	/* mdpdc */
95 		0x12554000,	/* mdotc */
96 		0xbabf7954,	/* mdcfg0 */
97 		0xdb328f64,	/* mdcfg1 */
98 		0x01ff00db,	/* mdcfg2 */
99 		0x00001680,	/* mdmisc */
100 		0x0f3c8000,	/* mdref */
101 		0x00002000,	/* mdrwd */
102 		0x00bf1023,	/* mdor */
103 		0x0000003f,	/* mdasp */
104 		0x0000022a,	/* mpodtctrl */
105 		0xa1390003,	/* mpzqhwctrl */
106 	};
107 
108 	mmdc_init(&mparam);
109 
110 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
111 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
112 	/* This will break-before-make MMU for DDR */
113 	update_early_mmu_table();
114 #endif
115 
116 	return 0;
117 }
118 
119 
120 int board_early_init_f(void)
121 {
122 	fsl_lsch2_early_init_f();
123 
124 	return 0;
125 }
126 
127 int board_init(void)
128 {
129 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
130 					CONFIG_SYS_CCI400_OFFSET);
131 	/*
132 	 * Set CCI-400 control override register to enable barrier
133 	 * transaction
134 	 */
135 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
136 
137 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
138 	erratum_a010315();
139 #endif
140 
141 #ifdef CONFIG_ENV_IS_NOWHERE
142 	gd->env_addr = (ulong)&default_environment[0];
143 #endif
144 
145 #ifdef CONFIG_FSL_CAAM
146 	sec_init();
147 #endif
148 
149 #ifdef CONFIG_FSL_LS_PPA
150 	ppa_init();
151 #endif
152 	return 0;
153 }
154 
155 #ifdef CONFIG_TARGET_LS1012ARDB
156 int esdhc_status_fixup(void *blob, const char *compat)
157 {
158 	char esdhc1_path[] = "/soc/esdhc@1580000";
159 	bool sdhc2_en = false;
160 	u8 mux_sdhc2;
161 	u8 io = 0;
162 
163 	i2c_set_bus_num(0);
164 
165 	/* IO1[7:3] is the field of board revision info. */
166 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
167 		printf("Error reading i2c boot information!\n");
168 		return 0;
169 	}
170 
171 	/* hwconfig method is used for RevD and later versions. */
172 	if ((io & SW_REV_MASK) <= SW_REV_D) {
173 #ifdef CONFIG_HWCONFIG
174 		if (hwconfig("esdhc1"))
175 			sdhc2_en = true;
176 #endif
177 	} else {
178 		/*
179 		 * The I2C IO-expander for mux select is used to control
180 		 * the muxing of various onboard interfaces.
181 		 *
182 		 * IO0[3:2] indicates SDHC2 interface demultiplexer
183 		 * select lines.
184 		 *	00 - SDIO wifi
185 		 *	01 - GPIO (to Arduino)
186 		 *	10 - eMMC Memory
187 		 *	11 - SPI
188 		 */
189 		if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
190 			printf("Error reading i2c boot information!\n");
191 			return 0;
192 		}
193 
194 		mux_sdhc2 = (io & 0x0c) >> 2;
195 		/* Enable SDHC2 only when use SDIO wifi and eMMC */
196 		if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
197 			sdhc2_en = true;
198 	}
199 	if (sdhc2_en)
200 		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
201 				 sizeof("okay"), 1);
202 	else
203 		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
204 				 sizeof("disabled"), 1);
205 	return 0;
206 }
207 #endif
208 
209 int ft_board_setup(void *blob, bd_t *bd)
210 {
211 	arch_fixup_fdt(blob);
212 
213 	ft_cpu_setup(blob, bd);
214 
215 	return 0;
216 }
217 
218 static int switch_to_bank1(void)
219 {
220 	u8 data;
221 	int ret;
222 
223 	i2c_set_bus_num(0);
224 
225 	data = 0xf4;
226 	ret = i2c_write(0x24, 0x3, 1, &data, 1);
227 	if (ret) {
228 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
229 		       0x24, 0x3, data);
230 	}
231 
232 	return ret;
233 }
234 
235 static int switch_to_bank2(void)
236 {
237 	u8 data;
238 	int ret;
239 
240 	i2c_set_bus_num(0);
241 
242 	data = 0xfc;
243 	ret = i2c_write(0x24, 0x7, 1, &data, 1);
244 	if (ret) {
245 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
246 		       0x24, 0x7, data);
247 		goto err;
248 	}
249 
250 	data = 0xf5;
251 	ret = i2c_write(0x24, 0x3, 1, &data, 1);
252 	if (ret) {
253 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
254 		       0x24, 0x3, data);
255 	}
256 err:
257 	return ret;
258 }
259 
260 static int convert_flash_bank(int bank)
261 {
262 	int ret = 0;
263 
264 	switch (bank) {
265 	case BOOT_FROM_UPPER_BANK:
266 		ret = switch_to_bank2();
267 		break;
268 	case BOOT_FROM_LOWER_BANK:
269 		ret = switch_to_bank1();
270 		break;
271 	default:
272 		ret = CMD_RET_USAGE;
273 		break;
274 	};
275 
276 	return ret;
277 }
278 
279 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
280 			  char * const argv[])
281 {
282 	if (argc != 2)
283 		return CMD_RET_USAGE;
284 	if (strcmp(argv[1], "1") == 0)
285 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
286 	else if (strcmp(argv[1], "2") == 0)
287 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
288 	else
289 		return CMD_RET_USAGE;
290 
291 	return 0;
292 }
293 
294 U_BOOT_CMD(
295 	boot_bank, 2, 0, flash_bank_cmd,
296 	"Flash bank Selection Control",
297 	"bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
298 );
299