1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #ifdef CONFIG_FSL_LS_PPA
13 #include <asm/arch/ppa.h>
14 #endif
15 #include <asm/arch/mmu.h>
16 #include <asm/arch/soc.h>
17 #include <hwconfig.h>
18 #include <ahci.h>
19 #include <mmc.h>
20 #include <scsi.h>
21 #include <fsl_esdhc.h>
22 #include <environment.h>
23 #include <fsl_mmdc.h>
24 #include <netdev.h>
25 #include <fsl_sec.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 int checkboard(void)
30 {
31 #ifdef CONFIG_TARGET_LS1012ARDB
32 	u8 in1;
33 
34 	puts("Board: LS1012ARDB ");
35 
36 	/* Initialize i2c early for Serial flash bank information */
37 	i2c_set_bus_num(0);
38 
39 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
40 		printf("Error reading i2c boot information!\n");
41 		return 0; /* Don't want to hang() on this error */
42 	}
43 
44 	puts("Version");
45 	switch (in1 & SW_REV_MASK) {
46 	case SW_REV_A:
47 		puts(": RevA");
48 		break;
49 	case SW_REV_B:
50 		puts(": RevB");
51 		break;
52 	case SW_REV_C:
53 		puts(": RevC");
54 		break;
55 	case SW_REV_C1:
56 		puts(": RevC1");
57 		break;
58 	case SW_REV_C2:
59 		puts(": RevC2");
60 		break;
61 	case SW_REV_D:
62 		puts(": RevD");
63 		break;
64 	case SW_REV_E:
65 		puts(": RevE");
66 		break;
67 	default:
68 		puts(": unknown");
69 		break;
70 	}
71 
72 	printf(", boot from QSPI");
73 	if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
74 		puts(": emu\n");
75 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
76 		puts(": bank1\n");
77 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
78 		puts(": bank2\n");
79 	else
80 		puts("unknown\n");
81 #else
82 
83 	puts("Board: LS1012A2G5RDB ");
84 #endif
85 	return 0;
86 }
87 
88 int dram_init(void)
89 {
90 	static const struct fsl_mmdc_info mparam = {
91 		0x05180000,	/* mdctl */
92 		0x00030035,	/* mdpdc */
93 		0x12554000,	/* mdotc */
94 		0xbabf7954,	/* mdcfg0 */
95 		0xdb328f64,	/* mdcfg1 */
96 		0x01ff00db,	/* mdcfg2 */
97 		0x00001680,	/* mdmisc */
98 		0x0f3c8000,	/* mdref */
99 		0x00002000,	/* mdrwd */
100 		0x00bf1023,	/* mdor */
101 		0x0000003f,	/* mdasp */
102 		0x0000022a,	/* mpodtctrl */
103 		0xa1390003,	/* mpzqhwctrl */
104 	};
105 
106 	mmdc_init(&mparam);
107 
108 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
109 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
110 	/* This will break-before-make MMU for DDR */
111 	update_early_mmu_table();
112 #endif
113 
114 	return 0;
115 }
116 
117 
118 int board_early_init_f(void)
119 {
120 	fsl_lsch2_early_init_f();
121 
122 	return 0;
123 }
124 
125 int board_init(void)
126 {
127 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
128 					CONFIG_SYS_CCI400_OFFSET);
129 	/*
130 	 * Set CCI-400 control override register to enable barrier
131 	 * transaction
132 	 */
133 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
134 
135 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
136 	erratum_a010315();
137 #endif
138 
139 #ifdef CONFIG_ENV_IS_NOWHERE
140 	gd->env_addr = (ulong)&default_environment[0];
141 #endif
142 
143 #ifdef CONFIG_FSL_CAAM
144 	sec_init();
145 #endif
146 
147 #ifdef CONFIG_FSL_LS_PPA
148 	ppa_init();
149 #endif
150 	return 0;
151 }
152 
153 #ifdef CONFIG_TARGET_LS1012ARDB
154 int esdhc_status_fixup(void *blob, const char *compat)
155 {
156 	char esdhc1_path[] = "/soc/esdhc@1580000";
157 	bool sdhc2_en = false;
158 	u8 mux_sdhc2;
159 	u8 io = 0;
160 
161 	i2c_set_bus_num(0);
162 
163 	/* IO1[7:3] is the field of board revision info. */
164 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
165 		printf("Error reading i2c boot information!\n");
166 		return 0;
167 	}
168 
169 	/* hwconfig method is used for RevD and later versions. */
170 	if ((io & SW_REV_MASK) <= SW_REV_D) {
171 #ifdef CONFIG_HWCONFIG
172 		if (hwconfig("esdhc1"))
173 			sdhc2_en = true;
174 #endif
175 	} else {
176 		/*
177 		 * The I2C IO-expander for mux select is used to control
178 		 * the muxing of various onboard interfaces.
179 		 *
180 		 * IO0[3:2] indicates SDHC2 interface demultiplexer
181 		 * select lines.
182 		 *	00 - SDIO wifi
183 		 *	01 - GPIO (to Arduino)
184 		 *	10 - eMMC Memory
185 		 *	11 - SPI
186 		 */
187 		if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
188 			printf("Error reading i2c boot information!\n");
189 			return 0;
190 		}
191 
192 		mux_sdhc2 = (io & 0x0c) >> 2;
193 		/* Enable SDHC2 only when use SDIO wifi and eMMC */
194 		if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
195 			sdhc2_en = true;
196 	}
197 	if (sdhc2_en)
198 		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
199 				 sizeof("okay"), 1);
200 	else
201 		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
202 				 sizeof("disabled"), 1);
203 	return 0;
204 }
205 #endif
206 
207 int ft_board_setup(void *blob, bd_t *bd)
208 {
209 	arch_fixup_fdt(blob);
210 
211 	ft_cpu_setup(blob, bd);
212 
213 	return 0;
214 }
215