1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #ifdef CONFIG_FSL_LS_PPA
12 #include <asm/arch/ppa.h>
13 #endif
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/soc.h>
16 #include <hwconfig.h>
17 #include <ahci.h>
18 #include <mmc.h>
19 #include <scsi.h>
20 #include <fsl_esdhc.h>
21 #include <environment.h>
22 #include <fsl_mmdc.h>
23 #include <netdev.h>
24 #include <fsl_sec.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 #define BOOT_FROM_UPPER_BANK	0x2
29 #define BOOT_FROM_LOWER_BANK	0x1
30 
31 int checkboard(void)
32 {
33 #ifdef CONFIG_TARGET_LS1012ARDB
34 	u8 in1;
35 
36 	puts("Board: LS1012ARDB ");
37 
38 	/* Initialize i2c early for Serial flash bank information */
39 	i2c_set_bus_num(0);
40 
41 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
42 		printf("Error reading i2c boot information!\n");
43 		return 0; /* Don't want to hang() on this error */
44 	}
45 
46 	puts("Version");
47 	switch (in1 & SW_REV_MASK) {
48 	case SW_REV_A:
49 		puts(": RevA");
50 		break;
51 	case SW_REV_B:
52 		puts(": RevB");
53 		break;
54 	case SW_REV_C:
55 		puts(": RevC");
56 		break;
57 	case SW_REV_C1:
58 		puts(": RevC1");
59 		break;
60 	case SW_REV_C2:
61 		puts(": RevC2");
62 		break;
63 	case SW_REV_D:
64 		puts(": RevD");
65 		break;
66 	case SW_REV_E:
67 		puts(": RevE");
68 		break;
69 	default:
70 		puts(": unknown");
71 		break;
72 	}
73 
74 	printf(", boot from QSPI");
75 	if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
76 		puts(": emu\n");
77 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
78 		puts(": bank1\n");
79 	else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
80 		puts(": bank2\n");
81 	else
82 		puts("unknown\n");
83 #else
84 
85 	puts("Board: LS1012A2G5RDB ");
86 #endif
87 	return 0;
88 }
89 
90 #ifdef CONFIG_TFABOOT
91 int dram_init(void)
92 {
93 	gd->ram_size = tfa_get_dram_size();
94 	if (!gd->ram_size)
95 		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
96 
97 	return 0;
98 }
99 #else
100 int dram_init(void)
101 {
102 #ifndef CONFIG_TFABOOT
103 	static const struct fsl_mmdc_info mparam = {
104 		0x05180000,	/* mdctl */
105 		0x00030035,	/* mdpdc */
106 		0x12554000,	/* mdotc */
107 		0xbabf7954,	/* mdcfg0 */
108 		0xdb328f64,	/* mdcfg1 */
109 		0x01ff00db,	/* mdcfg2 */
110 		0x00001680,	/* mdmisc */
111 		0x0f3c8000,	/* mdref */
112 		0x00002000,	/* mdrwd */
113 		0x00bf1023,	/* mdor */
114 		0x0000003f,	/* mdasp */
115 		0x0000022a,	/* mpodtctrl */
116 		0xa1390003,	/* mpzqhwctrl */
117 	};
118 
119 	mmdc_init(&mparam);
120 #endif
121 
122 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
123 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
124 	/* This will break-before-make MMU for DDR */
125 	update_early_mmu_table();
126 #endif
127 
128 	return 0;
129 }
130 #endif
131 
132 
133 int board_early_init_f(void)
134 {
135 	fsl_lsch2_early_init_f();
136 
137 	return 0;
138 }
139 
140 int board_init(void)
141 {
142 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
143 					CONFIG_SYS_CCI400_OFFSET);
144 	/*
145 	 * Set CCI-400 control override register to enable barrier
146 	 * transaction
147 	 */
148 	if (current_el() == 3)
149 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
150 
151 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
152 	erratum_a010315();
153 #endif
154 
155 #ifdef CONFIG_ENV_IS_NOWHERE
156 	gd->env_addr = (ulong)&default_environment[0];
157 #endif
158 
159 #ifdef CONFIG_FSL_CAAM
160 	sec_init();
161 #endif
162 
163 #ifdef CONFIG_FSL_LS_PPA
164 	ppa_init();
165 #endif
166 	return 0;
167 }
168 
169 #ifdef CONFIG_TARGET_LS1012ARDB
170 int esdhc_status_fixup(void *blob, const char *compat)
171 {
172 	char esdhc1_path[] = "/soc/esdhc@1580000";
173 	bool sdhc2_en = false;
174 	u8 mux_sdhc2;
175 	u8 io = 0;
176 
177 	i2c_set_bus_num(0);
178 
179 	/* IO1[7:3] is the field of board revision info. */
180 	if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
181 		printf("Error reading i2c boot information!\n");
182 		return 0;
183 	}
184 
185 	/* hwconfig method is used for RevD and later versions. */
186 	if ((io & SW_REV_MASK) <= SW_REV_D) {
187 #ifdef CONFIG_HWCONFIG
188 		if (hwconfig("esdhc1"))
189 			sdhc2_en = true;
190 #endif
191 	} else {
192 		/*
193 		 * The I2C IO-expander for mux select is used to control
194 		 * the muxing of various onboard interfaces.
195 		 *
196 		 * IO0[3:2] indicates SDHC2 interface demultiplexer
197 		 * select lines.
198 		 *	00 - SDIO wifi
199 		 *	01 - GPIO (to Arduino)
200 		 *	10 - eMMC Memory
201 		 *	11 - SPI
202 		 */
203 		if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
204 			printf("Error reading i2c boot information!\n");
205 			return 0;
206 		}
207 
208 		mux_sdhc2 = (io & 0x0c) >> 2;
209 		/* Enable SDHC2 only when use SDIO wifi and eMMC */
210 		if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
211 			sdhc2_en = true;
212 	}
213 	if (sdhc2_en)
214 		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
215 				 sizeof("okay"), 1);
216 	else
217 		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
218 				 sizeof("disabled"), 1);
219 	return 0;
220 }
221 #endif
222 
223 int ft_board_setup(void *blob, bd_t *bd)
224 {
225 	arch_fixup_fdt(blob);
226 
227 	ft_cpu_setup(blob, bd);
228 
229 	return 0;
230 }
231 
232 static int switch_to_bank1(void)
233 {
234 	u8 data;
235 	int ret;
236 
237 	i2c_set_bus_num(0);
238 
239 	data = 0xf4;
240 	ret = i2c_write(0x24, 0x3, 1, &data, 1);
241 	if (ret) {
242 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
243 		       0x24, 0x3, data);
244 	}
245 
246 	return ret;
247 }
248 
249 static int switch_to_bank2(void)
250 {
251 	u8 data;
252 	int ret;
253 
254 	i2c_set_bus_num(0);
255 
256 	data = 0xfc;
257 	ret = i2c_write(0x24, 0x7, 1, &data, 1);
258 	if (ret) {
259 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
260 		       0x24, 0x7, data);
261 		goto err;
262 	}
263 
264 	data = 0xf5;
265 	ret = i2c_write(0x24, 0x3, 1, &data, 1);
266 	if (ret) {
267 		printf("i2c write error to chip : %u, addr : %u, data : %u\n",
268 		       0x24, 0x3, data);
269 	}
270 err:
271 	return ret;
272 }
273 
274 static int convert_flash_bank(int bank)
275 {
276 	int ret = 0;
277 
278 	switch (bank) {
279 	case BOOT_FROM_UPPER_BANK:
280 		ret = switch_to_bank2();
281 		break;
282 	case BOOT_FROM_LOWER_BANK:
283 		ret = switch_to_bank1();
284 		break;
285 	default:
286 		ret = CMD_RET_USAGE;
287 		break;
288 	};
289 
290 	return ret;
291 }
292 
293 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
294 			  char * const argv[])
295 {
296 	if (argc != 2)
297 		return CMD_RET_USAGE;
298 	if (strcmp(argv[1], "1") == 0)
299 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
300 	else if (strcmp(argv[1], "2") == 0)
301 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
302 	else
303 		return CMD_RET_USAGE;
304 
305 	return 0;
306 }
307 
308 U_BOOT_CMD(
309 	boot_bank, 2, 0, flash_bank_cmd,
310 	"Flash bank Selection Control",
311 	"bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
312 );
313