1 /*
2  * Copyright 2015-2016 Freescale Semiconductor, Inc.
3  * Copyright 2017 NXP
4  *
5  * SPDX-License-Identifier:GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <dm.h>
10 #include <asm/io.h>
11 #include <netdev.h>
12 #include <fm_eth.h>
13 #include <fsl_mdio.h>
14 #include <malloc.h>
15 #include <asm/types.h>
16 #include <fsl_dtsec.h>
17 #include <asm/arch/soc.h>
18 #include <asm/arch-fsl-layerscape/config.h>
19 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
20 #include <asm/arch/fsl_serdes.h>
21 #include <net/pfe_eth/pfe_eth.h>
22 #include <dm/platform_data/pfe_dm_eth.h>
23 #include <i2c.h>
24 
25 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
26 
27 static inline void ls1012ardb_reset_phy(void)
28 {
29 #ifdef CONFIG_TARGET_LS1012ARDB
30 	/* Through reset IO expander reset both RGMII and SGMII PHYs */
31 	i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
32 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
33 	mdelay(10);
34 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
35 	mdelay(10);
36 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
37 	mdelay(50);
38 #endif
39 }
40 
41 int pfe_eth_board_init(struct udevice *dev)
42 {
43 	static int init_done;
44 	struct mii_dev *bus;
45 	struct pfe_mdio_info mac_mdio_info;
46 	struct pfe_eth_dev *priv = dev_get_priv(dev);
47 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
48 
49 	int srds_s1 = in_be32(&gur->rcwsr[4]) &
50 			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
51 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
52 
53 	if (!init_done) {
54 		ls1012ardb_reset_phy();
55 		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
56 		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
57 
58 		bus = pfe_mdio_init(&mac_mdio_info);
59 		if (!bus) {
60 			printf("Failed to register mdio\n");
61 			return -1;
62 		}
63 		init_done = 1;
64 	}
65 
66 	pfe_set_mdio(priv->gemac_port,
67 		     miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
68 
69 	switch (srds_s1) {
70 	case 0x3508:
71 		if (!priv->gemac_port) {
72 			/* MAC1 */
73 			pfe_set_phy_address_mode(priv->gemac_port,
74 						 CONFIG_PFE_EMAC1_PHY_ADDR,
75 						 PHY_INTERFACE_MODE_SGMII);
76 		} else {
77 			/* MAC2 */
78 			pfe_set_phy_address_mode(priv->gemac_port,
79 						 CONFIG_PFE_EMAC2_PHY_ADDR,
80 						 PHY_INTERFACE_MODE_RGMII_TXID);
81 		}
82 		break;
83 	case 0x2208:
84 		if (!priv->gemac_port) {
85 			/* MAC1 */
86 			pfe_set_phy_address_mode(priv->gemac_port,
87 						 CONFIG_PFE_EMAC1_PHY_ADDR,
88 						 PHY_INTERFACE_MODE_SGMII_2500);
89 		} else {
90 			/* MAC2 */
91 			pfe_set_phy_address_mode(priv->gemac_port,
92 						 CONFIG_PFE_EMAC2_PHY_ADDR,
93 						 PHY_INTERFACE_MODE_SGMII_2500);
94 		}
95 		break;
96 	default:
97 		printf("unsupported SerDes PRCTL= %d\n", srds_s1);
98 		break;
99 	}
100 	return 0;
101 }
102 
103 static struct pfe_eth_pdata pfe_pdata0 = {
104 	.pfe_eth_pdata_mac = {
105 		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
106 		.phy_interface = 0,
107 	},
108 
109 	.pfe_ddr_addr = {
110 		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
111 		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
112 	},
113 };
114 
115 static struct pfe_eth_pdata pfe_pdata1 = {
116 	.pfe_eth_pdata_mac = {
117 		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
118 		.phy_interface = 1,
119 	},
120 
121 	.pfe_ddr_addr = {
122 		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
123 		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
124 	},
125 };
126 
127 U_BOOT_DEVICE(ls1012a_pfe0) = {
128 	.name = "pfe_eth",
129 	.platdata = &pfe_pdata0,
130 };
131 
132 U_BOOT_DEVICE(ls1012a_pfe1) = {
133 	.name = "pfe_eth",
134 	.platdata = &pfe_pdata1,
135 };
136