1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29d044fcbSPrabhakar Kushwaha /* 39d044fcbSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 49d044fcbSPrabhakar Kushwaha */ 59d044fcbSPrabhakar Kushwaha 69d044fcbSPrabhakar Kushwaha #ifndef __LS1043AQDS_QIXIS_H__ 79d044fcbSPrabhakar Kushwaha #define __LS1043AQDS_QIXIS_H__ 89d044fcbSPrabhakar Kushwaha 99d044fcbSPrabhakar Kushwaha /* Definitions of QIXIS Registers for LS1043AQDS */ 109d044fcbSPrabhakar Kushwaha 119d044fcbSPrabhakar Kushwaha /* BRDCFG4[4:7] select EC1 and EC2 as a pair */ 129d044fcbSPrabhakar Kushwaha #define BRDCFG4_EMISEL_MASK 0xe0 137a8df8baSCalvin Johnson #define BRDCFG4_EMISEL_SHIFT 6 149d044fcbSPrabhakar Kushwaha 159d044fcbSPrabhakar Kushwaha /* SYSCLK */ 169d044fcbSPrabhakar Kushwaha #define QIXIS_SYSCLK_66 0x0 179d044fcbSPrabhakar Kushwaha #define QIXIS_SYSCLK_83 0x1 189d044fcbSPrabhakar Kushwaha #define QIXIS_SYSCLK_100 0x2 199d044fcbSPrabhakar Kushwaha #define QIXIS_SYSCLK_125 0x3 209d044fcbSPrabhakar Kushwaha #define QIXIS_SYSCLK_133 0x4 219d044fcbSPrabhakar Kushwaha 229d044fcbSPrabhakar Kushwaha /* DDRCLK */ 239d044fcbSPrabhakar Kushwaha #define QIXIS_DDRCLK_66 0x0 249d044fcbSPrabhakar Kushwaha #define QIXIS_DDRCLK_100 0x1 259d044fcbSPrabhakar Kushwaha #define QIXIS_DDRCLK_125 0x2 269d044fcbSPrabhakar Kushwaha #define QIXIS_DDRCLK_133 0x3 279d044fcbSPrabhakar Kushwaha 289d044fcbSPrabhakar Kushwaha /* BRDCFG2 - SD clock*/ 299d044fcbSPrabhakar Kushwaha #define QIXIS_SDCLK1_100 0x0 309d044fcbSPrabhakar Kushwaha #define QIXIS_SDCLK1_125 0x1 319d044fcbSPrabhakar Kushwaha #define QIXIS_SDCLK1_165 0x2 329d044fcbSPrabhakar Kushwaha #define QIXIS_SDCLK1_100_SP 0x3 339d044fcbSPrabhakar Kushwaha 349d044fcbSPrabhakar Kushwaha #endif 35