1 /*
2  * Copyright 2017 NXP
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #define ETH_1_1G_BUS_ID		0x1
8 #define ETH_1_1G_PHY_ID		0x1e
9 #define ETH_1_1G_MDIO_MUX	0x2
10 #define ETH_1G_MDIO_PHY_MASK	0xBFFFFFFD
11 #define ETH_1_1G_PHY_MODE	"sgmii"
12 #define ETH_2_1G_BUS_ID		0x1
13 #define ETH_2_1G_PHY_ID		0x1
14 #define ETH_2_1G_MDIO_MUX	0x1
15 #define ETH_2_1G_PHY_MODE	"rgmii"
16 
17 #define ETH_1_2_5G_BUS_ID	0x0
18 #define ETH_1_2_5G_PHY_ID	0x1
19 #define ETH_1_2_5G_MDIO_MUX	0x2
20 #define ETH_2_5G_MDIO_PHY_MASK	0xFFFFFFF9
21 #define ETH_2_5G_PHY_MODE	"sgmii-2500"
22 #define ETH_2_2_5G_BUS_ID	0x1
23 #define ETH_2_2_5G_PHY_ID	0x2
24 #define ETH_2_2_5G_MDIO_MUX	0x3
25 
26 #define SERDES_1_G_PROTOCOL	0x3508
27 #define SERDES_2_5_G_PROTOCOL	0x2205
28 
29 #define PFE_PROP_LEN		4
30 
31 #define ETH_1_PATH		"/pfe@04000000/ethernet@0"
32 #define ETH_1_MDIO		ETH_1_PATH "/mdio@0"
33 
34 #define ETH_2_PATH		"/pfe@04000000/ethernet@1"
35 #define ETH_2_MDIO		ETH_2_PATH "/mdio@0"
36 
37 #define NUM_ETH_NODE		2
38 
39 struct pfe_prop_val {
40 	int busid;
41 	int phyid;
42 	int mux_val;
43 	int phy_mask;
44 	char *phy_mode;
45 };
46