1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
15 #include <ahci.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <scsi.h>
19 #include <fm_eth.h>
20 #include <fsl_esdhc.h>
21 #include <fsl_mmdc.h>
22 #include <spl.h>
23 #include <netdev.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1012aqds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 int checkboard(void)
31 {
32 	char buf[64];
33 	u8 sw;
34 
35 	sw = QIXIS_READ(arch);
36 	printf("Board Arch: V%d, ", sw >> 4);
37 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
38 
39 	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
40 
41 	if (sw & QIXIS_LBMAP_ALTBANK)
42 		printf("flash: 2\n");
43 	else
44 		printf("flash: 1\n");
45 
46 	printf("FPGA: v%d (%s), build %d",
47 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
48 	       (int)qixis_read_minor());
49 
50 	/* the timestamp string contains "\n" at the end */
51 	printf(" on %s", qixis_read_time(buf));
52 	return 0;
53 }
54 
55 int dram_init(void)
56 {
57 	static const struct fsl_mmdc_info mparam = {
58 		0x05180000,	/* mdctl */
59 		0x00030035,	/* mdpdc */
60 		0x12554000,	/* mdotc */
61 		0xbabf7954,	/* mdcfg0 */
62 		0xdb328f64,	/* mdcfg1 */
63 		0x01ff00db,	/* mdcfg2 */
64 		0x00001680,	/* mdmisc */
65 		0x0f3c8000,	/* mdref */
66 		0x00002000,	/* mdrwd */
67 		0x00bf1023,	/* mdor */
68 		0x0000003f,	/* mdasp */
69 		0x0000022a,	/* mpodtctrl */
70 		0xa1390003,	/* mpzqhwctrl */
71 	};
72 
73 	mmdc_init(&mparam);
74 
75 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
76 
77 	return 0;
78 }
79 
80 int board_early_init_f(void)
81 {
82 	fsl_lsch2_early_init_f();
83 
84 	return 0;
85 }
86 
87 #ifdef CONFIG_MISC_INIT_R
88 int misc_init_r(void)
89 {
90 	u8 mux_sdhc_cd = 0x80;
91 
92 	i2c_set_bus_num(0);
93 
94 	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
95 	return 0;
96 }
97 #endif
98 
99 int board_init(void)
100 {
101 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
102 				   CONFIG_SYS_CCI400_ADDR;
103 
104 	/* Set CCI-400 control override register to enable barrier
105 	 * transaction */
106 	out_le32(&cci->ctrl_ord,
107 		 CCI400_CTRLORD_EN_BARRIER);
108 
109 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
110 	erratum_a010315();
111 #endif
112 
113 #ifdef CONFIG_ENV_IS_NOWHERE
114 	gd->env_addr = (ulong)&default_environment[0];
115 #endif
116 	return 0;
117 }
118 
119 int board_eth_init(bd_t *bis)
120 {
121 	return pci_eth_init(bis);
122 }
123 
124 #ifdef CONFIG_OF_BOARD_SETUP
125 int ft_board_setup(void *blob, bd_t *bd)
126 {
127 	arch_fixup_fdt(blob);
128 
129 	ft_cpu_setup(blob, bd);
130 
131 	return 0;
132 }
133 #endif
134