1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #ifdef CONFIG_FSL_LS_PPA 14 #include <asm/arch/ppa.h> 15 #endif 16 #include <asm/arch/fdt.h> 17 #include <asm/arch/mmu.h> 18 #include <asm/arch/soc.h> 19 #include <ahci.h> 20 #include <hwconfig.h> 21 #include <mmc.h> 22 #include <scsi.h> 23 #include <fm_eth.h> 24 #include <fsl_esdhc.h> 25 #include <fsl_mmdc.h> 26 #include <spl.h> 27 #include <netdev.h> 28 #include "../common/qixis.h" 29 #include "ls1012aqds_qixis.h" 30 #include "ls1012aqds_pfe.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 int checkboard(void) 35 { 36 char buf[64]; 37 u8 sw; 38 39 sw = QIXIS_READ(arch); 40 printf("Board Arch: V%d, ", sw >> 4); 41 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 42 43 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 44 45 if (sw & QIXIS_LBMAP_ALTBANK) 46 printf("flash: 2\n"); 47 else 48 printf("flash: 1\n"); 49 50 printf("FPGA: v%d (%s), build %d", 51 (int)QIXIS_READ(scver), qixis_read_tag(buf), 52 (int)qixis_read_minor()); 53 54 /* the timestamp string contains "\n" at the end */ 55 printf(" on %s", qixis_read_time(buf)); 56 return 0; 57 } 58 59 int dram_init(void) 60 { 61 static const struct fsl_mmdc_info mparam = { 62 0x05180000, /* mdctl */ 63 0x00030035, /* mdpdc */ 64 0x12554000, /* mdotc */ 65 0xbabf7954, /* mdcfg0 */ 66 0xdb328f64, /* mdcfg1 */ 67 0x01ff00db, /* mdcfg2 */ 68 0x00001680, /* mdmisc */ 69 0x0f3c8000, /* mdref */ 70 0x00002000, /* mdrwd */ 71 0x00bf1023, /* mdor */ 72 0x0000003f, /* mdasp */ 73 0x0000022a, /* mpodtctrl */ 74 0xa1390003, /* mpzqhwctrl */ 75 }; 76 77 mmdc_init(&mparam); 78 79 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 80 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 81 /* This will break-before-make MMU for DDR */ 82 update_early_mmu_table(); 83 #endif 84 85 return 0; 86 } 87 88 int board_early_init_f(void) 89 { 90 fsl_lsch2_early_init_f(); 91 92 return 0; 93 } 94 95 #ifdef CONFIG_MISC_INIT_R 96 int misc_init_r(void) 97 { 98 u8 mux_sdhc_cd = 0x80; 99 100 i2c_set_bus_num(0); 101 102 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); 103 return 0; 104 } 105 #endif 106 107 int board_init(void) 108 { 109 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 110 CONFIG_SYS_CCI400_OFFSET); 111 112 /* Set CCI-400 control override register to enable barrier 113 * transaction */ 114 out_le32(&cci->ctrl_ord, 115 CCI400_CTRLORD_EN_BARRIER); 116 117 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 118 erratum_a010315(); 119 #endif 120 121 #ifdef CONFIG_ENV_IS_NOWHERE 122 gd->env_addr = (ulong)&default_environment[0]; 123 #endif 124 125 #ifdef CONFIG_FSL_LS_PPA 126 ppa_init(); 127 #endif 128 return 0; 129 } 130 131 int esdhc_status_fixup(void *blob, const char *compat) 132 { 133 char esdhc0_path[] = "/soc/esdhc@1560000"; 134 char esdhc1_path[] = "/soc/esdhc@1580000"; 135 u8 card_id; 136 137 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 138 sizeof("okay"), 1); 139 140 /* 141 * The Presence Detect 2 register detects the installation 142 * of cards in various PCI Express or SGMII slots. 143 * 144 * STAT_PRS2[7:5]: Specifies the type of card installed in the 145 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. 146 */ 147 card_id = (QIXIS_READ(present2) & 0xe0) >> 5; 148 149 /* If no adapter is installed in SDHC2, disable SDHC2 */ 150 if (card_id == 0x7) 151 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 152 sizeof("disabled"), 1); 153 else 154 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 155 sizeof("okay"), 1); 156 return 0; 157 } 158 159 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, 160 char *enet_path, char *mdio_path) 161 { 162 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", 163 &prop_val.busid, PFE_PROP_LEN, 1); 164 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", 165 &prop_val.phyid, PFE_PROP_LEN, 1); 166 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", 167 &prop_val.mux_val, PFE_PROP_LEN, 1); 168 do_fixup_by_path(set_blob, enet_path, "phy-mode", 169 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); 170 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", 171 &prop_val.phy_mask, PFE_PROP_LEN, 1); 172 return 0; 173 } 174 175 static void fdt_fsl_fixup_of_pfe(void *blob) 176 { 177 int i = 0; 178 struct pfe_prop_val prop_val; 179 void *l_blob = blob; 180 181 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 182 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & 183 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; 184 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; 185 186 for (i = 0; i < NUM_ETH_NODE; i++) { 187 switch (srds_s1) { 188 case SERDES_1_G_PROTOCOL: 189 if (i == 0) { 190 prop_val.busid = cpu_to_fdt32( 191 ETH_1_1G_BUS_ID); 192 prop_val.phyid = cpu_to_fdt32( 193 ETH_1_1G_PHY_ID); 194 prop_val.mux_val = cpu_to_fdt32( 195 ETH_1_1G_MDIO_MUX); 196 prop_val.phy_mask = cpu_to_fdt32( 197 ETH_1G_MDIO_PHY_MASK); 198 prop_val.phy_mode = "sgmii"; 199 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 200 ETH_1_MDIO); 201 } else { 202 prop_val.busid = cpu_to_fdt32( 203 ETH_2_1G_BUS_ID); 204 prop_val.phyid = cpu_to_fdt32( 205 ETH_2_1G_PHY_ID); 206 prop_val.mux_val = cpu_to_fdt32( 207 ETH_2_1G_MDIO_MUX); 208 prop_val.phy_mask = cpu_to_fdt32( 209 ETH_1G_MDIO_PHY_MASK); 210 prop_val.phy_mode = "rgmii"; 211 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 212 ETH_2_MDIO); 213 } 214 break; 215 case SERDES_2_5_G_PROTOCOL: 216 if (i == 0) { 217 prop_val.busid = cpu_to_fdt32( 218 ETH_1_2_5G_BUS_ID); 219 prop_val.phyid = cpu_to_fdt32( 220 ETH_1_2_5G_PHY_ID); 221 prop_val.mux_val = cpu_to_fdt32( 222 ETH_1_2_5G_MDIO_MUX); 223 prop_val.phy_mask = cpu_to_fdt32( 224 ETH_2_5G_MDIO_PHY_MASK); 225 prop_val.phy_mode = "sgmii-2500"; 226 pfe_set_properties(l_blob, prop_val, ETH_1_PATH, 227 ETH_1_MDIO); 228 } else { 229 prop_val.busid = cpu_to_fdt32( 230 ETH_2_2_5G_BUS_ID); 231 prop_val.phyid = cpu_to_fdt32( 232 ETH_2_2_5G_PHY_ID); 233 prop_val.mux_val = cpu_to_fdt32( 234 ETH_2_2_5G_MDIO_MUX); 235 prop_val.phy_mask = cpu_to_fdt32( 236 ETH_2_5G_MDIO_PHY_MASK); 237 prop_val.phy_mode = "sgmii-2500"; 238 pfe_set_properties(l_blob, prop_val, ETH_2_PATH, 239 ETH_2_MDIO); 240 } 241 break; 242 default: 243 printf("serdes:[%d]\n", srds_s1); 244 } 245 } 246 } 247 248 #ifdef CONFIG_OF_BOARD_SETUP 249 int ft_board_setup(void *blob, bd_t *bd) 250 { 251 arch_fixup_fdt(blob); 252 253 ft_cpu_setup(blob, bd); 254 fdt_fsl_fixup_of_pfe(blob); 255 256 return 0; 257 } 258 #endif 259