19d044fcbSPrabhakar Kushwaha /* 29d044fcbSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 39d044fcbSPrabhakar Kushwaha * 49d044fcbSPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 59d044fcbSPrabhakar Kushwaha */ 69d044fcbSPrabhakar Kushwaha 79d044fcbSPrabhakar Kushwaha #include <common.h> 89d044fcbSPrabhakar Kushwaha #include <i2c.h> 99d044fcbSPrabhakar Kushwaha #include <fdt_support.h> 109d044fcbSPrabhakar Kushwaha #include <asm/io.h> 119d044fcbSPrabhakar Kushwaha #include <asm/arch/clock.h> 129d044fcbSPrabhakar Kushwaha #include <asm/arch/fsl_serdes.h> 139d044fcbSPrabhakar Kushwaha #include <asm/arch/fdt.h> 149d044fcbSPrabhakar Kushwaha #include <asm/arch/soc.h> 159d044fcbSPrabhakar Kushwaha #include <ahci.h> 169d044fcbSPrabhakar Kushwaha #include <hwconfig.h> 179d044fcbSPrabhakar Kushwaha #include <mmc.h> 189d044fcbSPrabhakar Kushwaha #include <scsi.h> 199d044fcbSPrabhakar Kushwaha #include <fm_eth.h> 209d044fcbSPrabhakar Kushwaha #include <fsl_esdhc.h> 219d044fcbSPrabhakar Kushwaha #include <fsl_mmdc.h> 229d044fcbSPrabhakar Kushwaha #include <spl.h> 239d044fcbSPrabhakar Kushwaha #include <netdev.h> 249d044fcbSPrabhakar Kushwaha 259d044fcbSPrabhakar Kushwaha #include "../common/qixis.h" 269d044fcbSPrabhakar Kushwaha #include "ls1012aqds_qixis.h" 279d044fcbSPrabhakar Kushwaha 289d044fcbSPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 299d044fcbSPrabhakar Kushwaha 309d044fcbSPrabhakar Kushwaha static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 319d044fcbSPrabhakar Kushwaha { 329d044fcbSPrabhakar Kushwaha int timeout = 1000; 339d044fcbSPrabhakar Kushwaha 349d044fcbSPrabhakar Kushwaha out_be32(ptr, value); 359d044fcbSPrabhakar Kushwaha 369d044fcbSPrabhakar Kushwaha while (in_be32(ptr) & bits) { 379d044fcbSPrabhakar Kushwaha udelay(100); 389d044fcbSPrabhakar Kushwaha timeout--; 399d044fcbSPrabhakar Kushwaha } 409d044fcbSPrabhakar Kushwaha if (timeout <= 0) 419d044fcbSPrabhakar Kushwaha puts("Error: wait for clear timeout.\n"); 429d044fcbSPrabhakar Kushwaha } 439d044fcbSPrabhakar Kushwaha 449d044fcbSPrabhakar Kushwaha int checkboard(void) 459d044fcbSPrabhakar Kushwaha { 469d044fcbSPrabhakar Kushwaha char buf[64]; 479d044fcbSPrabhakar Kushwaha u8 sw; 489d044fcbSPrabhakar Kushwaha 499d044fcbSPrabhakar Kushwaha sw = QIXIS_READ(arch); 509d044fcbSPrabhakar Kushwaha printf("Board Arch: V%d, ", sw >> 4); 519d044fcbSPrabhakar Kushwaha printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 529d044fcbSPrabhakar Kushwaha 539d044fcbSPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 549d044fcbSPrabhakar Kushwaha 559d044fcbSPrabhakar Kushwaha if (sw & QIXIS_LBMAP_ALTBANK) 569d044fcbSPrabhakar Kushwaha printf("flash: 2\n"); 579d044fcbSPrabhakar Kushwaha else 589d044fcbSPrabhakar Kushwaha printf("flash: 1\n"); 599d044fcbSPrabhakar Kushwaha 609d044fcbSPrabhakar Kushwaha printf("FPGA: v%d (%s), build %d", 619d044fcbSPrabhakar Kushwaha (int)QIXIS_READ(scver), qixis_read_tag(buf), 629d044fcbSPrabhakar Kushwaha (int)qixis_read_minor()); 639d044fcbSPrabhakar Kushwaha 649d044fcbSPrabhakar Kushwaha /* the timestamp string contains "\n" at the end */ 659d044fcbSPrabhakar Kushwaha printf(" on %s", qixis_read_time(buf)); 669d044fcbSPrabhakar Kushwaha return 0; 679d044fcbSPrabhakar Kushwaha } 689d044fcbSPrabhakar Kushwaha 699d044fcbSPrabhakar Kushwaha void mmdc_init(void) 709d044fcbSPrabhakar Kushwaha { 719d044fcbSPrabhakar Kushwaha struct mmdc_p_regs *mmdc = 729d044fcbSPrabhakar Kushwaha (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; 739d044fcbSPrabhakar Kushwaha 749d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 759d044fcbSPrabhakar Kushwaha 769d044fcbSPrabhakar Kushwaha /* configure timing parms */ 779d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); 789d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); 799d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); 809d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); 819d044fcbSPrabhakar Kushwaha 829d044fcbSPrabhakar Kushwaha /* other parms */ 839d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); 849d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); 859d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); 869d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); 879d044fcbSPrabhakar Kushwaha 889d044fcbSPrabhakar Kushwaha /* out of reset delays */ 899d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); 909d044fcbSPrabhakar Kushwaha 919d044fcbSPrabhakar Kushwaha /* physical parms */ 929d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); 939d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); 949d044fcbSPrabhakar Kushwaha 959d044fcbSPrabhakar Kushwaha /* Enable MMDC */ 969d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); 979d044fcbSPrabhakar Kushwaha 989d044fcbSPrabhakar Kushwaha /* dram init sequence: update MRs */ 999d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | 1009d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); 1019d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 1029d044fcbSPrabhakar Kushwaha CMD_BANK_ADDR_3)); 1039d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 1049d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 1059d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | 1069d044fcbSPrabhakar Kushwaha CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | 1079d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); 1089d044fcbSPrabhakar Kushwaha 1099d044fcbSPrabhakar Kushwaha /* dram init sequence: ZQCL */ 1109d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 1119d044fcbSPrabhakar Kushwaha CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); 1129d044fcbSPrabhakar Kushwaha set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 1139d044fcbSPrabhakar Kushwaha CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, 1149d044fcbSPrabhakar Kushwaha FORCE_ZQ_AUTO_CALIBRATION); 1159d044fcbSPrabhakar Kushwaha 1169d044fcbSPrabhakar Kushwaha /* Calibrations now: wr lvl */ 1179d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | 1189d044fcbSPrabhakar Kushwaha CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 1199d044fcbSPrabhakar Kushwaha CMD_BANK_ADDR_1)); 1209d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); 1219d044fcbSPrabhakar Kushwaha set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); 1229d044fcbSPrabhakar Kushwaha 1239d044fcbSPrabhakar Kushwaha mdelay(1); 1249d044fcbSPrabhakar Kushwaha 1259d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 1269d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 1279d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 1289d044fcbSPrabhakar Kushwaha 1299d044fcbSPrabhakar Kushwaha mdelay(1); 1309d044fcbSPrabhakar Kushwaha 1319d044fcbSPrabhakar Kushwaha /* Calibrations now: Read DQS gating calibration */ 1329d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 1339d044fcbSPrabhakar Kushwaha CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 1349d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 1359d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 1369d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 1379d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); 1389d044fcbSPrabhakar Kushwaha set_wait_for_bits_clear(&mmdc->mpdgctrl0, 1399d044fcbSPrabhakar Kushwaha AUTO_RD_DQS_GATING_CALIBRATION_EN, 1409d044fcbSPrabhakar Kushwaha AUTO_RD_DQS_GATING_CALIBRATION_EN); 1419d044fcbSPrabhakar Kushwaha 1429d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 1439d044fcbSPrabhakar Kushwaha CMD_BANK_ADDR_3)); 1449d044fcbSPrabhakar Kushwaha 1459d044fcbSPrabhakar Kushwaha /* Calibrations now: Read calibration */ 1469d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 1479d044fcbSPrabhakar Kushwaha CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 1489d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 1499d044fcbSPrabhakar Kushwaha CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 1509d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 1519d044fcbSPrabhakar Kushwaha set_wait_for_bits_clear(&mmdc->mprddlhwctl, 1529d044fcbSPrabhakar Kushwaha AUTO_RD_CALIBRATION_EN, 1539d044fcbSPrabhakar Kushwaha AUTO_RD_CALIBRATION_EN); 1549d044fcbSPrabhakar Kushwaha 1559d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 1569d044fcbSPrabhakar Kushwaha CMD_BANK_ADDR_3)); 1579d044fcbSPrabhakar Kushwaha 1589d044fcbSPrabhakar Kushwaha /* PD, SR */ 1599d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); 1609d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); 1619d044fcbSPrabhakar Kushwaha 1629d044fcbSPrabhakar Kushwaha /* refresh scheme */ 1639d044fcbSPrabhakar Kushwaha set_wait_for_bits_clear(&mmdc->mdref, 1649d044fcbSPrabhakar Kushwaha CONFIG_SYS_MMDC_CORE_REFRESH_CTL, 1659d044fcbSPrabhakar Kushwaha START_REFRESH); 1669d044fcbSPrabhakar Kushwaha 1679d044fcbSPrabhakar Kushwaha /* disable CON_REQ */ 1689d044fcbSPrabhakar Kushwaha out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); 1699d044fcbSPrabhakar Kushwaha } 1709d044fcbSPrabhakar Kushwaha 1719d044fcbSPrabhakar Kushwaha int dram_init(void) 1729d044fcbSPrabhakar Kushwaha { 1739d044fcbSPrabhakar Kushwaha mmdc_init(); 1749d044fcbSPrabhakar Kushwaha 1759d044fcbSPrabhakar Kushwaha gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 1769d044fcbSPrabhakar Kushwaha 1779d044fcbSPrabhakar Kushwaha return 0; 1789d044fcbSPrabhakar Kushwaha } 1799d044fcbSPrabhakar Kushwaha 1809d044fcbSPrabhakar Kushwaha int board_early_init_f(void) 1819d044fcbSPrabhakar Kushwaha { 1829d044fcbSPrabhakar Kushwaha fsl_lsch2_early_init_f(); 1839d044fcbSPrabhakar Kushwaha 1849d044fcbSPrabhakar Kushwaha return 0; 1859d044fcbSPrabhakar Kushwaha } 1869d044fcbSPrabhakar Kushwaha 1879d044fcbSPrabhakar Kushwaha #ifdef CONFIG_MISC_INIT_R 1889d044fcbSPrabhakar Kushwaha int misc_init_r(void) 1899d044fcbSPrabhakar Kushwaha { 1909d044fcbSPrabhakar Kushwaha u8 mux_sdhc_cd = 0x80; 1919d044fcbSPrabhakar Kushwaha 1929d044fcbSPrabhakar Kushwaha i2c_set_bus_num(0); 1939d044fcbSPrabhakar Kushwaha 1949d044fcbSPrabhakar Kushwaha i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); 1959d044fcbSPrabhakar Kushwaha return 0; 1969d044fcbSPrabhakar Kushwaha } 1979d044fcbSPrabhakar Kushwaha #endif 1989d044fcbSPrabhakar Kushwaha 1999d044fcbSPrabhakar Kushwaha int board_init(void) 2009d044fcbSPrabhakar Kushwaha { 2019d044fcbSPrabhakar Kushwaha struct ccsr_cci400 *cci = (struct ccsr_cci400 *) 2029d044fcbSPrabhakar Kushwaha CONFIG_SYS_CCI400_ADDR; 2039d044fcbSPrabhakar Kushwaha 2049d044fcbSPrabhakar Kushwaha /* Set CCI-400 control override register to enable barrier 2059d044fcbSPrabhakar Kushwaha * transaction */ 2069d044fcbSPrabhakar Kushwaha out_le32(&cci->ctrl_ord, 2079d044fcbSPrabhakar Kushwaha CCI400_CTRLORD_EN_BARRIER); 2089d044fcbSPrabhakar Kushwaha 209*b392a6d4SHou Zhiqiang #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 210*b392a6d4SHou Zhiqiang erratum_a010315(); 211*b392a6d4SHou Zhiqiang #endif 212*b392a6d4SHou Zhiqiang 2139d044fcbSPrabhakar Kushwaha #ifdef CONFIG_ENV_IS_NOWHERE 2149d044fcbSPrabhakar Kushwaha gd->env_addr = (ulong)&default_environment[0]; 2159d044fcbSPrabhakar Kushwaha #endif 2169d044fcbSPrabhakar Kushwaha return 0; 2179d044fcbSPrabhakar Kushwaha } 2189d044fcbSPrabhakar Kushwaha 2199d044fcbSPrabhakar Kushwaha int board_eth_init(bd_t *bis) 2209d044fcbSPrabhakar Kushwaha { 2219d044fcbSPrabhakar Kushwaha return pci_eth_init(bis); 2229d044fcbSPrabhakar Kushwaha } 2239d044fcbSPrabhakar Kushwaha 2249d044fcbSPrabhakar Kushwaha #ifdef CONFIG_OF_BOARD_SETUP 2259d044fcbSPrabhakar Kushwaha int ft_board_setup(void *blob, bd_t *bd) 2269d044fcbSPrabhakar Kushwaha { 2279d044fcbSPrabhakar Kushwaha arch_fixup_fdt(blob); 2289d044fcbSPrabhakar Kushwaha 2299d044fcbSPrabhakar Kushwaha ft_cpu_setup(blob, bd); 2309d044fcbSPrabhakar Kushwaha 2319d044fcbSPrabhakar Kushwaha return 0; 2329d044fcbSPrabhakar Kushwaha } 2339d044fcbSPrabhakar Kushwaha #endif 234