1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <fsl_csu.h> 15 #include <environment.h> 16 #include <fsl_mmdc.h> 17 #include <netdev.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 22 { 23 int timeout = 1000; 24 25 out_be32(ptr, value); 26 27 while (in_be32(ptr) & bits) { 28 udelay(100); 29 timeout--; 30 } 31 if (timeout <= 0) 32 puts("Error: wait for clear timeout.\n"); 33 } 34 35 int checkboard(void) 36 { 37 puts("Board: LS1012AFRDM "); 38 39 return 0; 40 } 41 42 void mmdc_init(void) 43 { 44 struct mmdc_p_regs *mmdc = 45 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; 46 47 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 48 49 /* configure timing parms */ 50 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); 51 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); 52 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); 53 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); 54 55 /* other parms */ 56 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); 57 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); 58 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); 59 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); 60 61 /* out of reset delays */ 62 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); 63 64 /* physical parms */ 65 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); 66 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); 67 68 /* Enable MMDC */ 69 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); 70 71 /* dram init sequence: update MRs */ 72 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | 73 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); 74 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 75 CMD_BANK_ADDR_3)); 76 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 77 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 78 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | 79 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | 80 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); 81 82 /* dram init sequence: ZQCL */ 83 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 84 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); 85 set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 86 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, 87 FORCE_ZQ_AUTO_CALIBRATION); 88 89 /* Calibrations now: wr lvl */ 90 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | 91 CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 92 CMD_BANK_ADDR_1)); 93 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); 94 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); 95 96 mdelay(1); 97 98 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 99 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 100 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 101 102 mdelay(1); 103 104 /* Calibrations now: Read DQS gating calibration */ 105 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 106 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 107 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 108 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 109 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 110 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); 111 set_wait_for_bits_clear(&mmdc->mpdgctrl0, 112 AUTO_RD_DQS_GATING_CALIBRATION_EN, 113 AUTO_RD_DQS_GATING_CALIBRATION_EN); 114 115 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 116 CMD_BANK_ADDR_3)); 117 118 /* Calibrations now: Read calibration */ 119 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 120 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 121 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 122 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 123 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 124 set_wait_for_bits_clear(&mmdc->mprddlhwctl, 125 AUTO_RD_CALIBRATION_EN, 126 AUTO_RD_CALIBRATION_EN); 127 128 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 129 CMD_BANK_ADDR_3)); 130 131 /* PD, SR */ 132 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); 133 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); 134 135 /* refresh scheme */ 136 set_wait_for_bits_clear(&mmdc->mdref, 137 CONFIG_SYS_MMDC_CORE_REFRESH_CTL, 138 START_REFRESH); 139 140 /* disable CON_REQ */ 141 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); 142 } 143 144 int dram_init(void) 145 { 146 mmdc_init(); 147 148 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 149 150 return 0; 151 } 152 153 int board_eth_init(bd_t *bis) 154 { 155 return pci_eth_init(bis); 156 } 157 158 int board_early_init_f(void) 159 { 160 fsl_lsch2_early_init_f(); 161 162 return 0; 163 } 164 165 int board_init(void) 166 { 167 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 168 /* 169 * Set CCI-400 control override register to enable barrier 170 * transaction 171 */ 172 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 173 174 #ifdef CONFIG_ENV_IS_NOWHERE 175 gd->env_addr = (ulong)&default_environment[0]; 176 #endif 177 178 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 179 enable_layerscape_ns_access(); 180 #endif 181 182 return 0; 183 } 184 185 int ft_board_setup(void *blob, bd_t *bd) 186 { 187 arch_fixup_fdt(blob); 188 189 ft_cpu_setup(blob, bd); 190 191 return 0; 192 } 193