1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <netdev.h> 11 #include <fm_eth.h> 12 #include <fsl_mdio.h> 13 #include <malloc.h> 14 #include <asm/types.h> 15 #include <fsl_dtsec.h> 16 #include <asm/arch/soc.h> 17 #include <asm/arch-fsl-layerscape/config.h> 18 #include <asm/arch-fsl-layerscape/immap_lsch2.h> 19 #include <asm/arch/fsl_serdes.h> 20 #include <net/pfe_eth/pfe_eth.h> 21 #include <dm/platform_data/pfe_dm_eth.h> 22 23 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" 24 #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" 25 26 #define MASK_ETH_PHY_RST 0x00000100 27 28 static inline void ls1012afrdm_reset_phy(void) 29 { 30 unsigned int val; 31 struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); 32 33 setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); 34 35 val = in_be32(&pgpio->gpdat); 36 setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); 37 mdelay(10); 38 39 val = in_be32(&pgpio->gpdat); 40 setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); 41 mdelay(50); 42 } 43 44 int pfe_eth_board_init(struct udevice *dev) 45 { 46 static int init_done; 47 struct mii_dev *bus; 48 struct pfe_mdio_info mac_mdio_info; 49 struct pfe_eth_dev *priv = dev_get_priv(dev); 50 51 if (!init_done) { 52 ls1012afrdm_reset_phy(); 53 54 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; 55 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; 56 57 bus = pfe_mdio_init(&mac_mdio_info); 58 if (!bus) { 59 printf("Failed to register mdio\n"); 60 return -1; 61 } 62 63 init_done = 1; 64 } 65 66 if (priv->gemac_port) { 67 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; 68 mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; 69 bus = pfe_mdio_init(&mac_mdio_info); 70 if (!bus) { 71 printf("Failed to register mdio\n"); 72 return -1; 73 } 74 } 75 76 pfe_set_mdio(priv->gemac_port, 77 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); 78 if (!priv->gemac_port) 79 /* MAC1 */ 80 pfe_set_phy_address_mode(priv->gemac_port, 81 CONFIG_PFE_EMAC1_PHY_ADDR, 82 PHY_INTERFACE_MODE_SGMII); 83 else 84 /* MAC2 */ 85 pfe_set_phy_address_mode(priv->gemac_port, 86 CONFIG_PFE_EMAC2_PHY_ADDR, 87 PHY_INTERFACE_MODE_SGMII); 88 return 0; 89 } 90 91 static struct pfe_eth_pdata pfe_pdata0 = { 92 .pfe_eth_pdata_mac = { 93 .iobase = (phys_addr_t)EMAC1_BASE_ADDR, 94 .phy_interface = 0, 95 }, 96 97 .pfe_ddr_addr = { 98 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, 99 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, 100 }, 101 }; 102 103 static struct pfe_eth_pdata pfe_pdata1 = { 104 .pfe_eth_pdata_mac = { 105 .iobase = (phys_addr_t)EMAC2_BASE_ADDR, 106 .phy_interface = 1, 107 }, 108 109 .pfe_ddr_addr = { 110 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, 111 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, 112 }, 113 }; 114 115 U_BOOT_DEVICE(ls1012a_pfe0) = { 116 .name = "pfe_eth", 117 .platdata = &pfe_pdata0, 118 }; 119 120 U_BOOT_DEVICE(ls1012a_pfe1) = { 121 .name = "pfe_eth", 122 .platdata = &pfe_pdata1, 123 }; 124