1 /* 2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <netdev.h> 12 #include <fm_eth.h> 13 #include <fsl_mdio.h> 14 #include <malloc.h> 15 #include <asm/types.h> 16 #include <fsl_dtsec.h> 17 #include <asm/arch/soc.h> 18 #include <asm/arch-fsl-layerscape/config.h> 19 #include <asm/arch-fsl-layerscape/immap_lsch2.h> 20 #include <asm/arch/fsl_serdes.h> 21 #include <net/pfe_eth/pfe_eth.h> 22 #include <dm/platform_data/pfe_dm_eth.h> 23 24 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" 25 #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" 26 27 #define MASK_ETH_PHY_RST 0x00000100 28 29 static inline void ls1012afrdm_reset_phy(void) 30 { 31 unsigned int val; 32 struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); 33 34 setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); 35 36 val = in_be32(&pgpio->gpdat); 37 setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); 38 mdelay(10); 39 40 val = in_be32(&pgpio->gpdat); 41 setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); 42 mdelay(50); 43 } 44 45 int pfe_eth_board_init(struct udevice *dev) 46 { 47 static int init_done; 48 struct mii_dev *bus; 49 struct pfe_mdio_info mac_mdio_info; 50 struct pfe_eth_dev *priv = dev_get_priv(dev); 51 52 if (!init_done) { 53 ls1012afrdm_reset_phy(); 54 55 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; 56 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; 57 58 bus = pfe_mdio_init(&mac_mdio_info); 59 if (!bus) { 60 printf("Failed to register mdio\n"); 61 return -1; 62 } 63 64 init_done = 1; 65 } 66 67 if (priv->gemac_port) { 68 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; 69 mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; 70 bus = pfe_mdio_init(&mac_mdio_info); 71 if (!bus) { 72 printf("Failed to register mdio\n"); 73 return -1; 74 } 75 } 76 77 pfe_set_mdio(priv->gemac_port, 78 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); 79 if (!priv->gemac_port) 80 /* MAC1 */ 81 pfe_set_phy_address_mode(priv->gemac_port, 82 CONFIG_PFE_EMAC1_PHY_ADDR, 83 PHY_INTERFACE_MODE_SGMII); 84 else 85 /* MAC2 */ 86 pfe_set_phy_address_mode(priv->gemac_port, 87 CONFIG_PFE_EMAC2_PHY_ADDR, 88 PHY_INTERFACE_MODE_SGMII); 89 return 0; 90 } 91 92 static struct pfe_eth_pdata pfe_pdata0 = { 93 .pfe_eth_pdata_mac = { 94 .iobase = (phys_addr_t)EMAC1_BASE_ADDR, 95 .phy_interface = 0, 96 }, 97 98 .pfe_ddr_addr = { 99 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, 100 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, 101 }, 102 }; 103 104 static struct pfe_eth_pdata pfe_pdata1 = { 105 .pfe_eth_pdata_mac = { 106 .iobase = (phys_addr_t)EMAC2_BASE_ADDR, 107 .phy_interface = 1, 108 }, 109 110 .pfe_ddr_addr = { 111 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, 112 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, 113 }, 114 }; 115 116 U_BOOT_DEVICE(ls1012a_pfe0) = { 117 .name = "pfe_eth", 118 .platdata = &pfe_pdata0, 119 }; 120 121 U_BOOT_DEVICE(ls1012a_pfe1) = { 122 .name = "pfe_eth", 123 .platdata = &pfe_pdata1, 124 }; 125