1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * This file handles the board muxing between the Fman Ethernet MACs and 26 * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference 27 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 28 * provided by the standard Freescale four-port SGMII riser card. The 10Gb 29 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans 30 * and 5 1G interfaces and 10G interface per FMan. Based on the options in 31 * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. 32 * 33 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control 34 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is 35 * always the same (0). The value for SGMII depends on which slot the riser is 36 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, 37 * the value is based on which slot the XAUI is inserted in. 38 * 39 * The SERDES configuration is used to determine where the SGMII and XAUI cards 40 * exist, and also which Fman's MACs are routed to which PHYs. So for a given 41 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed 42 * to PHYs dynamically. 43 * 44 * 45 * This file also updates the device tree in three ways: 46 * 47 * 1) The status of each virtual MDIO node that is referenced by an Ethernet 48 * node is set to "okay". 49 * 50 * 2) The phy-handle property of each active Ethernet MAC node is set to the 51 * appropriate PHY node. 52 * 53 * 3) The "mux value" for each virtual MDIO node is set to the correct value, 54 * if necessary. Some virtual MDIO nodes do not have configurable mux 55 * values, so those values are hard-coded in the DTS. On the HYDRA board, 56 * the virtual MDIO node for the SGMII card needs to be updated. 57 * 58 * For all this to work, the device tree needs to have the following: 59 * 60 * 1) An alias for each PHY node that an Ethernet node could be routed to. 61 * 62 * 2) An alias for each real and virtual MDIO node that is disabled by default 63 * and might need to be enabled, and also might need to have its mux-value 64 * updated. 65 */ 66 67 #include <common.h> 68 #include <netdev.h> 69 #include <asm/fsl_serdes.h> 70 #include <fm_eth.h> 71 #include <fsl_mdio.h> 72 #include <malloc.h> 73 #include <fdt_support.h> 74 #include <asm/fsl_dtsec.h> 75 76 #include "../common/ngpixis.h" 77 #include "../common/fman.h" 78 79 #ifdef CONFIG_FMAN_ENET 80 81 #define BRDCFG1_EMI1_SEL_MASK 0x70 82 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 83 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 84 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 85 #define BRDCFG1_EMI1_SEL_SLOT6 0x40 86 #define BRDCFG1_EMI1_SEL_SLOT7 0x50 87 #define BRDCFG1_EMI1_SEL_SLOT3 0x60 88 #define BRDCFG1_EMI1_SEL_RGMII 0x00 89 #define BRDCFG1_EMI1_EN 0x08 90 #define BRDCFG1_EMI2_SEL_MASK 0x06 91 #define BRDCFG1_EMI2_SEL_SLOT1 0x00 92 #define BRDCFG1_EMI2_SEL_SLOT2 0x02 93 94 #define BRDCFG2_REG_GPIO_SEL 0x20 95 96 /* 97 * BRDCFG1 mask and value for each MAC 98 * 99 * This array contains the BRDCFG1 values (in mask/val format) that route the 100 * MDIO bus to a particular RGMII or SGMII PHY. 101 */ 102 static struct { 103 u8 mask; 104 u8 val; 105 } mdio_mux[NUM_FM_PORTS]; 106 107 /* 108 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 109 * that the mapping must be determined dynamically, or that the lane maps to 110 * something other than a board slot 111 */ 112 static u8 lane_to_slot[] = { 113 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 114 }; 115 116 /* 117 * Set the board muxing for a given MAC 118 * 119 * The MDIO layer calls this function every time it wants to talk to a PHY. 120 */ 121 void super_hydra_mux_mdio(u8 mask, u8 val) 122 { 123 clrsetbits_8(&pixis->brdcfg1, mask, val); 124 } 125 126 struct super_hydra_mdio { 127 u8 mask; 128 u8 val; 129 struct mii_dev *realbus; 130 }; 131 132 static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, 133 int regnum) 134 { 135 struct super_hydra_mdio *priv = bus->priv; 136 137 super_hydra_mux_mdio(priv->mask, priv->val); 138 139 return priv->realbus->read(priv->realbus, addr, devad, regnum); 140 } 141 142 static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, 143 int regnum, u16 value) 144 { 145 struct super_hydra_mdio *priv = bus->priv; 146 147 super_hydra_mux_mdio(priv->mask, priv->val); 148 149 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 150 } 151 152 static int super_hydra_mdio_reset(struct mii_dev *bus) 153 { 154 struct super_hydra_mdio *priv = bus->priv; 155 156 return priv->realbus->reset(priv->realbus); 157 } 158 159 static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) 160 { 161 struct mii_dev *bus = miiphy_get_dev_by_name(name); 162 struct super_hydra_mdio *priv = bus->priv; 163 164 priv->mask = mask; 165 priv->val = val; 166 } 167 168 static int super_hydra_mdio_init(char *realbusname, char *fakebusname) 169 { 170 struct super_hydra_mdio *hmdio; 171 struct mii_dev *bus = mdio_alloc(); 172 173 if (!bus) { 174 printf("Failed to allocate Hydra MDIO bus\n"); 175 return -1; 176 } 177 178 hmdio = malloc(sizeof(*hmdio)); 179 if (!hmdio) { 180 printf("Failed to allocate Hydra private data\n"); 181 free(bus); 182 return -1; 183 } 184 185 bus->read = super_hydra_mdio_read; 186 bus->write = super_hydra_mdio_write; 187 bus->reset = super_hydra_mdio_reset; 188 sprintf(bus->name, fakebusname); 189 190 hmdio->realbus = miiphy_get_dev_by_name(realbusname); 191 192 if (!hmdio->realbus) { 193 printf("No bus with name %s\n", realbusname); 194 free(bus); 195 free(hmdio); 196 return -1; 197 } 198 199 bus->priv = hmdio; 200 201 return mdio_register(bus); 202 } 203 204 /* 205 * Given the following ... 206 * 207 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 208 * compatible string and 'addr' physical address) 209 * 210 * 2) An Fman port 211 * 212 * ... update the phy-handle property of the Ethernet node to point to the 213 * right PHY. This assumes that we already know the PHY for each port. That 214 * information is stored in mdio_mux[]. 215 * 216 * The offset of the Fman Ethernet node is also passed in for convenience, but 217 * it is not used. 218 * 219 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 220 * Inside the Fman, "ports" are things that connect to MACs. We only call them 221 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 222 * and ports are the same thing. 223 */ 224 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 225 enum fm_port port, int offset) 226 { 227 enum srds_prtcl device; 228 int lane, slot, phy; 229 char alias[32]; 230 231 /* RGMII and XGMII are already mapped correctly in the DTS */ 232 233 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 234 device = serdes_device_from_fm_port(port); 235 lane = serdes_get_first_lane(device); 236 slot = lane_to_slot[lane]; 237 phy = fm_info_get_phy_address(port); 238 239 sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); 240 fdt_set_phy_handle(fdt, compat, addr, alias); 241 } 242 } 243 244 #define PIXIS_SW2_LANE_23_SEL 0x80 245 #define PIXIS_SW2_LANE_45_SEL 0x40 246 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30 247 #define PIXIS_SW2_LANE_67_SEL_5 0x00 248 #define PIXIS_SW2_LANE_67_SEL_6 0x20 249 #define PIXIS_SW2_LANE_67_SEL_7 0x10 250 #define PIXIS_SW2_LANE_8_SEL 0x08 251 #define PIXIS_SW2_LANE_1617_SEL 0x04 252 #define PIXIS_SW11_LANE_9_SEL 0x04 253 /* 254 * Initialize the lane_to_slot[] array. 255 * 256 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board 257 * slots is hard-coded. On the Hydra board, however, the mapping is controlled 258 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically 259 * initialized. 260 */ 261 static void initialize_lane_to_slot(void) 262 { 263 u8 sw2 = in_8(&PIXIS_SW(2)); 264 /* SW11 appears in the programming model as SW9 */ 265 u8 sw11 = in_8(&PIXIS_SW(9)); 266 267 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; 268 lane_to_slot[3] = lane_to_slot[2]; 269 270 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; 271 lane_to_slot[5] = lane_to_slot[4]; 272 273 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { 274 case PIXIS_SW2_LANE_67_SEL_5: 275 lane_to_slot[6] = 5; 276 break; 277 case PIXIS_SW2_LANE_67_SEL_6: 278 lane_to_slot[6] = 6; 279 break; 280 case PIXIS_SW2_LANE_67_SEL_7: 281 lane_to_slot[6] = 7; 282 break; 283 } 284 lane_to_slot[7] = lane_to_slot[6]; 285 286 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; 287 lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; 288 289 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; 290 lane_to_slot[17] = lane_to_slot[16]; 291 } 292 293 #endif /* #ifdef CONFIG_FMAN_ENET */ 294 295 /* 296 * Configure the status for the virtual MDIO nodes 297 * 298 * Rather than create the virtual MDIO nodes from scratch for each active 299 * virtual MDIO, we expect the DTS to have the nodes defined already, and we 300 * only enable the ones that are actually active. 301 * 302 * We assume that the DTS already hard-codes the status for all the 303 * virtual MDIO nodes to "disabled", so all we need to do is enable the 304 * active ones. 305 */ 306 void fdt_fixup_board_enet(void *fdt) 307 { 308 #ifdef CONFIG_FMAN_ENET 309 enum fm_port i; 310 int lane, slot; 311 312 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 313 int idx = i - FM1_DTSEC1; 314 315 switch (fm_info_get_enet_if(i)) { 316 case PHY_INTERFACE_MODE_SGMII: 317 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 318 if (lane >= 0) { 319 char alias[32]; 320 321 slot = lane_to_slot[lane]; 322 sprintf(alias, "hydra_sg_slot%u", slot); 323 fdt_status_okay_by_alias(fdt, alias); 324 debug("Enabled MDIO node %s (slot %i)\n", 325 alias, slot); 326 } 327 break; 328 case PHY_INTERFACE_MODE_RGMII: 329 fdt_status_okay_by_alias(fdt, "hydra_rg"); 330 debug("Enabled MDIO node hydra_rg\n"); 331 break; 332 default: 333 break; 334 } 335 } 336 337 lane = serdes_get_first_lane(XAUI_FM1); 338 if (lane >= 0) { 339 char alias[32]; 340 341 slot = lane_to_slot[lane]; 342 sprintf(alias, "hydra_xg_slot%u", slot); 343 fdt_status_okay_by_alias(fdt, alias); 344 debug("Enabled MDIO node %s (slot %i)\n", alias, slot); 345 } 346 347 #if CONFIG_SYS_NUM_FMAN == 2 348 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 349 int idx = i - FM2_DTSEC1; 350 351 switch (fm_info_get_enet_if(i)) { 352 case PHY_INTERFACE_MODE_SGMII: 353 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 354 if (lane >= 0) { 355 char alias[32]; 356 357 slot = lane_to_slot[lane]; 358 sprintf(alias, "hydra_sg_slot%u", slot); 359 fdt_status_okay_by_alias(fdt, alias); 360 debug("Enabled MDIO node %s (slot %i)\n", 361 alias, slot); 362 } 363 break; 364 case PHY_INTERFACE_MODE_RGMII: 365 fdt_status_okay_by_alias(fdt, "hydra_rg"); 366 debug("Enabled MDIO node hydra_rg\n"); 367 break; 368 default: 369 break; 370 } 371 } 372 373 lane = serdes_get_first_lane(XAUI_FM2); 374 if (lane >= 0) { 375 char alias[32]; 376 377 slot = lane_to_slot[lane]; 378 sprintf(alias, "hydra_xg_slot%u", slot); 379 fdt_status_okay_by_alias(fdt, alias); 380 debug("Enabled MDIO node %s (slot %i)\n", alias, slot); 381 } 382 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 383 #endif /* CONFIG_FMAN_ENET */ 384 } 385 386 /* 387 * Mapping of SerDes Protocol to MDIO MUX value and PHY address. 388 * 389 * Fman 1: 390 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 391 * Mux Phy | Mux Phy | Mux Phy | Mux Phy 392 * Value Addr | Value Addr | Value Addr | Value Addr 393 * 0x00 2 1c | 2 1d | 2 1e | 2 1f 394 * 0x01 | | 6 1c | 395 * 0x02 | | 3 1c | 3 1d 396 * 0x03 2 1c | 2 1d | 2 1e | 2 1f 397 * 0x04 2 1c | 2 1d | 2 1e | 2 1f 398 * 0x05 | | 3 1c | 3 1d 399 * 0x06 2 1c | 2 1d | 2 1e | 2 1f 400 * 0x07 | | 6 1c | 401 * 0x11 2 1c | 2 1d | 2 1e | 2 1f 402 * 0x2a 2 | | 2 1e | 2 1f 403 * 0x34 6 1c | 6 1d | 4 1e | 4 1f 404 * 0x35 | | 3 1c | 3 1d 405 * 0x36 6 1c | 6 1d | 4 1e | 4 1f 406 * | | | 407 * Fman 2: | | | 408 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 409 * EMI1 | EMI1 | EMI1 | EMI1 410 * Mux Phy | Mux Phy | Mux Phy | Mux Phy 411 * Value Addr | Value Addr | Value Addr | Value Addr 412 * 0x00 | | 6 1c | 6 1d 413 * 0x01 | | | 414 * 0x02 | | 6 1c | 6 1d 415 * 0x03 3 1c | 3 1d | 6 1c | 6 1d 416 * 0x04 3 1c | 3 1d | 6 1c | 6 1d 417 * 0x05 | | 6 1c | 6 1d 418 * 0x06 | | 6 1c | 6 1d 419 * 0x07 | | | 420 * 0x11 | | | 421 * 0x2a | | | 422 * 0x34 | | | 423 * 0x35 | | | 424 * 0x36 | | | 425 */ 426 427 int board_eth_init(bd_t *bis) 428 { 429 #ifdef CONFIG_FMAN_ENET 430 struct fsl_pq_mdio_info dtsec_mdio_info; 431 struct tgec_mdio_info tgec_mdio_info; 432 unsigned int i, slot; 433 int lane; 434 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 435 int srds_prtcl = (in_be32(&gur->rcwsr[4]) & 436 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 437 438 printf("Initializing Fman\n"); 439 440 initialize_lane_to_slot(); 441 442 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ 443 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); 444 445 memset(mdio_mux, 0, sizeof(mdio_mux)); 446 447 dtsec_mdio_info.regs = 448 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 449 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 450 451 /* Register the real 1G MDIO bus */ 452 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 453 454 tgec_mdio_info.regs = 455 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 456 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 457 458 /* Register the real 10G MDIO bus */ 459 fm_tgec_mdio_init(bis, &tgec_mdio_info); 460 461 /* Register the three virtual MDIO front-ends */ 462 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 463 "SUPER_HYDRA_RGMII_MDIO"); 464 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 465 "SUPER_HYDRA_FM1_SGMII_MDIO"); 466 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 467 "SUPER_HYDRA_FM2_SGMII_MDIO"); 468 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, 469 "SUPER_HYDRA_FM1_TGEC_MDIO"); 470 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, 471 "SUPER_HYDRA_FM2_TGEC_MDIO"); 472 473 /* 474 * Program the DTSEC PHY addresses assuming that they are all SGMII. 475 * For any DTSEC that's RGMII, we'll override its PHY address later. 476 * We assume that DTSEC5 is only used for RGMII. 477 */ 478 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 479 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 480 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 481 482 #if (CONFIG_SYS_NUM_FMAN == 2) 483 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 484 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 485 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 486 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 487 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 488 #endif 489 490 switch (srds_prtcl) { 491 case 0: 492 case 3: 493 case 4: 494 case 6: 495 case 0x11: 496 case 0x2a: 497 case 0x34: 498 case 0x36: 499 fm_info_set_phy_address(FM1_DTSEC3, 500 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 501 fm_info_set_phy_address(FM1_DTSEC4, 502 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 503 break; 504 case 1: 505 case 2: 506 case 5: 507 case 7: 508 case 0x35: 509 fm_info_set_phy_address(FM1_DTSEC3, 510 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 511 fm_info_set_phy_address(FM1_DTSEC4, 512 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 513 break; 514 default: 515 printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); 516 break; 517 } 518 519 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 520 int idx = i - FM1_DTSEC1; 521 522 switch (fm_info_get_enet_if(i)) { 523 case PHY_INTERFACE_MODE_SGMII: 524 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 525 if (lane < 0) 526 break; 527 slot = lane_to_slot[lane]; 528 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 529 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 530 idx + 1, slot); 531 switch (slot) { 532 case 1: 533 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 534 BRDCFG1_EMI1_EN; 535 break; 536 case 2: 537 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 538 BRDCFG1_EMI1_EN; 539 break; 540 case 3: 541 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | 542 BRDCFG1_EMI1_EN; 543 break; 544 case 5: 545 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 546 BRDCFG1_EMI1_EN; 547 break; 548 case 6: 549 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 550 BRDCFG1_EMI1_EN; 551 break; 552 case 7: 553 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 554 BRDCFG1_EMI1_EN; 555 break; 556 }; 557 558 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", 559 mdio_mux[i].mask, mdio_mux[i].val); 560 fm_info_set_mdio(i, 561 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); 562 break; 563 case PHY_INTERFACE_MODE_RGMII: 564 /* 565 * FM1 DTSEC5 is routed via EC1 to the first on-board 566 * RGMII port. FM2 DTSEC5 is routed via EC2 to the 567 * second on-board RGMII port. The other DTSECs cannot 568 * be routed to RGMII. 569 */ 570 debug("FM1@DTSEC%u is RGMII at address %u\n", 571 idx + 1, 0); 572 fm_info_set_phy_address(i, 0); 573 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 574 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 575 BRDCFG1_EMI1_EN; 576 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", 577 mdio_mux[i].mask, mdio_mux[i].val); 578 fm_info_set_mdio(i, 579 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); 580 break; 581 case PHY_INTERFACE_MODE_NONE: 582 fm_info_set_phy_address(i, 0); 583 break; 584 default: 585 printf("Fman1: DTSEC%u set to unknown interface %i\n", 586 idx + 1, fm_info_get_enet_if(i)); 587 fm_info_set_phy_address(i, 0); 588 break; 589 } 590 } 591 592 /* 593 * For 10G, we only support one XAUI card per Fman. If present, then we 594 * force its routing and never touch those bits again, which removes the 595 * need for Linux to do any muxing. This works because of the way 596 * BRDCFG1 is defined, but it's a bit hackish. 597 * 598 * The PHY address for the XAUI card depends on which slot it's in. The 599 * macros we use imply that the PHY address is based on which FM, but 600 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 601 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 602 * check the actual slot and just use the macros as-is, even though 603 * the P3041 and P5020 only have one Fman. 604 */ 605 lane = serdes_get_first_lane(XAUI_FM1); 606 if (lane >= 0) { 607 debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); 608 mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; 609 mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; 610 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", 611 mdio_mux[i].mask, mdio_mux[i].val); 612 } 613 614 fm_info_set_mdio(FM1_10GEC1, 615 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); 616 617 #if (CONFIG_SYS_NUM_FMAN == 2) 618 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 619 int idx = i - FM2_DTSEC1; 620 621 switch (fm_info_get_enet_if(i)) { 622 case PHY_INTERFACE_MODE_SGMII: 623 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 624 if (lane < 0) 625 break; 626 slot = lane_to_slot[lane]; 627 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 628 debug("FM2@DTSEC%u expects SGMII in slot %u\n", 629 idx + 1, slot); 630 switch (slot) { 631 case 1: 632 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 633 BRDCFG1_EMI1_EN; 634 break; 635 case 2: 636 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 637 BRDCFG1_EMI1_EN; 638 break; 639 case 3: 640 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | 641 BRDCFG1_EMI1_EN; 642 break; 643 case 5: 644 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 645 BRDCFG1_EMI1_EN; 646 break; 647 case 6: 648 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 649 BRDCFG1_EMI1_EN; 650 break; 651 case 7: 652 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 653 BRDCFG1_EMI1_EN; 654 break; 655 }; 656 657 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", 658 mdio_mux[i].mask, mdio_mux[i].val); 659 fm_info_set_mdio(i, 660 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); 661 break; 662 case PHY_INTERFACE_MODE_RGMII: 663 /* 664 * FM1 DTSEC5 is routed via EC1 to the first on-board 665 * RGMII port. FM2 DTSEC5 is routed via EC2 to the 666 * second on-board RGMII port. The other DTSECs cannot 667 * be routed to RGMII. 668 */ 669 debug("FM2@DTSEC%u is RGMII at address %u\n", 670 idx + 1, 1); 671 fm_info_set_phy_address(i, 1); 672 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 673 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 674 BRDCFG1_EMI1_EN; 675 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", 676 mdio_mux[i].mask, mdio_mux[i].val); 677 fm_info_set_mdio(i, 678 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); 679 break; 680 case PHY_INTERFACE_MODE_NONE: 681 fm_info_set_phy_address(i, 0); 682 break; 683 default: 684 printf("Fman2: DTSEC%u set to unknown interface %i\n", 685 idx + 1, fm_info_get_enet_if(i)); 686 fm_info_set_phy_address(i, 0); 687 break; 688 } 689 } 690 691 /* 692 * For 10G, we only support one XAUI card per Fman. If present, then we 693 * force its routing and never touch those bits again, which removes the 694 * need for Linux to do any muxing. This works because of the way 695 * BRDCFG1 is defined, but it's a bit hackish. 696 * 697 * The PHY address for the XAUI card depends on which slot it's in. The 698 * macros we use imply that the PHY address is based on which FM, but 699 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 700 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 701 * check the actual slot and just use the macros as-is, even though 702 * the P3041 and P5020 only have one Fman. 703 */ 704 lane = serdes_get_first_lane(XAUI_FM2); 705 if (lane >= 0) { 706 debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); 707 mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; 708 mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; 709 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", 710 mdio_mux[i].mask, mdio_mux[i].val); 711 } 712 713 fm_info_set_mdio(FM2_10GEC1, 714 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); 715 716 #endif 717 718 cpu_eth_init(bis); 719 #endif 720 721 return pci_eth_init(bis); 722 } 723