1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file handles the board muxing between the Fman Ethernet MACs and 10 * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference 11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb 13 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans 14 * and 5 1G interfaces and 10G interface per FMan. Based on the options in 15 * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. 16 * 17 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control 18 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is 19 * always the same (0). The value for SGMII depends on which slot the riser is 20 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, 21 * the value is based on which slot the XAUI is inserted in. 22 * 23 * The SERDES configuration is used to determine where the SGMII and XAUI cards 24 * exist, and also which Fman's MACs are routed to which PHYs. So for a given 25 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed 26 * to PHYs dynamically. 27 * 28 * 29 * This file also updates the device tree in three ways: 30 * 31 * 1) The status of each virtual MDIO node that is referenced by an Ethernet 32 * node is set to "okay". 33 * 34 * 2) The phy-handle property of each active Ethernet MAC node is set to the 35 * appropriate PHY node. 36 * 37 * 3) The "mux value" for each virtual MDIO node is set to the correct value, 38 * if necessary. Some virtual MDIO nodes do not have configurable mux 39 * values, so those values are hard-coded in the DTS. On the HYDRA board, 40 * the virtual MDIO node for the SGMII card needs to be updated. 41 * 42 * For all this to work, the device tree needs to have the following: 43 * 44 * 1) An alias for each PHY node that an Ethernet node could be routed to. 45 * 46 * 2) An alias for each real and virtual MDIO node that is disabled by default 47 * and might need to be enabled, and also might need to have its mux-value 48 * updated. 49 */ 50 51 #include <common.h> 52 #include <netdev.h> 53 #include <asm/fsl_serdes.h> 54 #include <fm_eth.h> 55 #include <fsl_mdio.h> 56 #include <malloc.h> 57 #include <fdt_support.h> 58 #include <asm/fsl_dtsec.h> 59 60 #include "../common/ngpixis.h" 61 #include "../common/fman.h" 62 63 #ifdef CONFIG_FMAN_ENET 64 65 #define BRDCFG1_EMI1_SEL_MASK 0x70 66 #define BRDCFG1_EMI1_SEL_SLOT1 0x10 67 #define BRDCFG1_EMI1_SEL_SLOT2 0x20 68 #define BRDCFG1_EMI1_SEL_SLOT5 0x30 69 #define BRDCFG1_EMI1_SEL_SLOT6 0x40 70 #define BRDCFG1_EMI1_SEL_SLOT7 0x50 71 #define BRDCFG1_EMI1_SEL_SLOT3 0x60 72 #define BRDCFG1_EMI1_SEL_RGMII 0x00 73 #define BRDCFG1_EMI1_EN 0x08 74 #define BRDCFG1_EMI2_SEL_MASK 0x06 75 #define BRDCFG1_EMI2_SEL_SLOT1 0x00 76 #define BRDCFG1_EMI2_SEL_SLOT2 0x02 77 78 #define BRDCFG2_REG_GPIO_SEL 0x20 79 80 /* 81 * BRDCFG1 mask and value for each MAC 82 * 83 * This array contains the BRDCFG1 values (in mask/val format) that route the 84 * MDIO bus to a particular RGMII or SGMII PHY. 85 */ 86 static struct { 87 u8 mask; 88 u8 val; 89 } mdio_mux[NUM_FM_PORTS]; 90 91 /* 92 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means 93 * that the mapping must be determined dynamically, or that the lane maps to 94 * something other than a board slot 95 */ 96 static u8 lane_to_slot[] = { 97 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 98 }; 99 100 /* 101 * Set the board muxing for a given MAC 102 * 103 * The MDIO layer calls this function every time it wants to talk to a PHY. 104 */ 105 void super_hydra_mux_mdio(u8 mask, u8 val) 106 { 107 clrsetbits_8(&pixis->brdcfg1, mask, val); 108 } 109 110 struct super_hydra_mdio { 111 u8 mask; 112 u8 val; 113 struct mii_dev *realbus; 114 }; 115 116 static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, 117 int regnum) 118 { 119 struct super_hydra_mdio *priv = bus->priv; 120 121 super_hydra_mux_mdio(priv->mask, priv->val); 122 123 return priv->realbus->read(priv->realbus, addr, devad, regnum); 124 } 125 126 static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, 127 int regnum, u16 value) 128 { 129 struct super_hydra_mdio *priv = bus->priv; 130 131 super_hydra_mux_mdio(priv->mask, priv->val); 132 133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 134 } 135 136 static int super_hydra_mdio_reset(struct mii_dev *bus) 137 { 138 struct super_hydra_mdio *priv = bus->priv; 139 140 return priv->realbus->reset(priv->realbus); 141 } 142 143 static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) 144 { 145 struct mii_dev *bus = miiphy_get_dev_by_name(name); 146 struct super_hydra_mdio *priv = bus->priv; 147 148 priv->mask = mask; 149 priv->val = val; 150 } 151 152 static int super_hydra_mdio_init(char *realbusname, char *fakebusname) 153 { 154 struct super_hydra_mdio *hmdio; 155 struct mii_dev *bus = mdio_alloc(); 156 157 if (!bus) { 158 printf("Failed to allocate Hydra MDIO bus\n"); 159 return -1; 160 } 161 162 hmdio = malloc(sizeof(*hmdio)); 163 if (!hmdio) { 164 printf("Failed to allocate Hydra private data\n"); 165 free(bus); 166 return -1; 167 } 168 169 bus->read = super_hydra_mdio_read; 170 bus->write = super_hydra_mdio_write; 171 bus->reset = super_hydra_mdio_reset; 172 sprintf(bus->name, fakebusname); 173 174 hmdio->realbus = miiphy_get_dev_by_name(realbusname); 175 176 if (!hmdio->realbus) { 177 printf("No bus with name %s\n", realbusname); 178 free(bus); 179 free(hmdio); 180 return -1; 181 } 182 183 bus->priv = hmdio; 184 185 return mdio_register(bus); 186 } 187 188 /* 189 * Given the following ... 190 * 191 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' 192 * compatible string and 'addr' physical address) 193 * 194 * 2) An Fman port 195 * 196 * ... update the phy-handle property of the Ethernet node to point to the 197 * right PHY. This assumes that we already know the PHY for each port. That 198 * information is stored in mdio_mux[]. 199 * 200 * The offset of the Fman Ethernet node is also passed in for convenience, but 201 * it is not used. 202 * 203 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. 204 * Inside the Fman, "ports" are things that connect to MACs. We only call them 205 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs 206 * and ports are the same thing. 207 */ 208 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 209 enum fm_port port, int offset) 210 { 211 enum srds_prtcl device; 212 int lane, slot, phy; 213 char alias[32]; 214 215 /* RGMII and XGMII are already mapped correctly in the DTS */ 216 217 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 218 device = serdes_device_from_fm_port(port); 219 lane = serdes_get_first_lane(device); 220 slot = lane_to_slot[lane]; 221 phy = fm_info_get_phy_address(port); 222 223 sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); 224 fdt_set_phy_handle(fdt, compat, addr, alias); 225 } 226 } 227 228 #define PIXIS_SW2_LANE_23_SEL 0x80 229 #define PIXIS_SW2_LANE_45_SEL 0x40 230 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30 231 #define PIXIS_SW2_LANE_67_SEL_5 0x00 232 #define PIXIS_SW2_LANE_67_SEL_6 0x20 233 #define PIXIS_SW2_LANE_67_SEL_7 0x10 234 #define PIXIS_SW2_LANE_8_SEL 0x08 235 #define PIXIS_SW2_LANE_1617_SEL 0x04 236 #define PIXIS_SW11_LANE_9_SEL 0x04 237 /* 238 * Initialize the lane_to_slot[] array. 239 * 240 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board 241 * slots is hard-coded. On the Hydra board, however, the mapping is controlled 242 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically 243 * initialized. 244 */ 245 static void initialize_lane_to_slot(void) 246 { 247 u8 sw2 = in_8(&PIXIS_SW(2)); 248 /* SW11 appears in the programming model as SW9 */ 249 u8 sw11 = in_8(&PIXIS_SW(9)); 250 251 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; 252 lane_to_slot[3] = lane_to_slot[2]; 253 254 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; 255 lane_to_slot[5] = lane_to_slot[4]; 256 257 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { 258 case PIXIS_SW2_LANE_67_SEL_5: 259 lane_to_slot[6] = 5; 260 break; 261 case PIXIS_SW2_LANE_67_SEL_6: 262 lane_to_slot[6] = 6; 263 break; 264 case PIXIS_SW2_LANE_67_SEL_7: 265 lane_to_slot[6] = 7; 266 break; 267 } 268 lane_to_slot[7] = lane_to_slot[6]; 269 270 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; 271 lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; 272 273 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; 274 lane_to_slot[17] = lane_to_slot[16]; 275 } 276 277 #endif /* #ifdef CONFIG_FMAN_ENET */ 278 279 /* 280 * Configure the status for the virtual MDIO nodes 281 * 282 * Rather than create the virtual MDIO nodes from scratch for each active 283 * virtual MDIO, we expect the DTS to have the nodes defined already, and we 284 * only enable the ones that are actually active. 285 * 286 * We assume that the DTS already hard-codes the status for all the 287 * virtual MDIO nodes to "disabled", so all we need to do is enable the 288 * active ones. 289 */ 290 void fdt_fixup_board_enet(void *fdt) 291 { 292 #ifdef CONFIG_FMAN_ENET 293 enum fm_port i; 294 int lane, slot; 295 296 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 297 int idx = i - FM1_DTSEC1; 298 299 switch (fm_info_get_enet_if(i)) { 300 case PHY_INTERFACE_MODE_SGMII: 301 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 302 if (lane >= 0) { 303 char alias[32]; 304 305 slot = lane_to_slot[lane]; 306 sprintf(alias, "hydra_sg_slot%u", slot); 307 fdt_status_okay_by_alias(fdt, alias); 308 debug("Enabled MDIO node %s (slot %i)\n", 309 alias, slot); 310 } 311 break; 312 case PHY_INTERFACE_MODE_RGMII: 313 fdt_status_okay_by_alias(fdt, "hydra_rg"); 314 debug("Enabled MDIO node hydra_rg\n"); 315 break; 316 default: 317 break; 318 } 319 } 320 321 lane = serdes_get_first_lane(XAUI_FM1); 322 if (lane >= 0) { 323 char alias[32]; 324 325 slot = lane_to_slot[lane]; 326 sprintf(alias, "hydra_xg_slot%u", slot); 327 fdt_status_okay_by_alias(fdt, alias); 328 debug("Enabled MDIO node %s (slot %i)\n", alias, slot); 329 } 330 331 #if CONFIG_SYS_NUM_FMAN == 2 332 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 333 int idx = i - FM2_DTSEC1; 334 335 switch (fm_info_get_enet_if(i)) { 336 case PHY_INTERFACE_MODE_SGMII: 337 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 338 if (lane >= 0) { 339 char alias[32]; 340 341 slot = lane_to_slot[lane]; 342 sprintf(alias, "hydra_sg_slot%u", slot); 343 fdt_status_okay_by_alias(fdt, alias); 344 debug("Enabled MDIO node %s (slot %i)\n", 345 alias, slot); 346 } 347 break; 348 case PHY_INTERFACE_MODE_RGMII: 349 fdt_status_okay_by_alias(fdt, "hydra_rg"); 350 debug("Enabled MDIO node hydra_rg\n"); 351 break; 352 default: 353 break; 354 } 355 } 356 357 lane = serdes_get_first_lane(XAUI_FM2); 358 if (lane >= 0) { 359 char alias[32]; 360 361 slot = lane_to_slot[lane]; 362 sprintf(alias, "hydra_xg_slot%u", slot); 363 fdt_status_okay_by_alias(fdt, alias); 364 debug("Enabled MDIO node %s (slot %i)\n", alias, slot); 365 } 366 #endif /* CONFIG_SYS_NUM_FMAN == 2 */ 367 #endif /* CONFIG_FMAN_ENET */ 368 } 369 370 /* 371 * Mapping of SerDes Protocol to MDIO MUX value and PHY address. 372 * 373 * Fman 1: 374 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 375 * Mux Phy | Mux Phy | Mux Phy | Mux Phy 376 * Value Addr | Value Addr | Value Addr | Value Addr 377 * 0x00 2 1c | 2 1d | 2 1e | 2 1f 378 * 0x01 | | 6 1c | 379 * 0x02 | | 3 1c | 3 1d 380 * 0x03 2 1c | 2 1d | 2 1e | 2 1f 381 * 0x04 2 1c | 2 1d | 2 1e | 2 1f 382 * 0x05 | | 3 1c | 3 1d 383 * 0x06 2 1c | 2 1d | 2 1e | 2 1f 384 * 0x07 | | 6 1c | 385 * 0x11 2 1c | 2 1d | 2 1e | 2 1f 386 * 0x2a 2 | | 2 1e | 2 1f 387 * 0x34 6 1c | 6 1d | 4 1e | 4 1f 388 * 0x35 | | 3 1c | 3 1d 389 * 0x36 6 1c | 6 1d | 4 1e | 4 1f 390 * | | | 391 * Fman 2: | | | 392 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 393 * EMI1 | EMI1 | EMI1 | EMI1 394 * Mux Phy | Mux Phy | Mux Phy | Mux Phy 395 * Value Addr | Value Addr | Value Addr | Value Addr 396 * 0x00 | | 6 1c | 6 1d 397 * 0x01 | | | 398 * 0x02 | | 6 1c | 6 1d 399 * 0x03 3 1c | 3 1d | 6 1c | 6 1d 400 * 0x04 3 1c | 3 1d | 6 1c | 6 1d 401 * 0x05 | | 6 1c | 6 1d 402 * 0x06 | | 6 1c | 6 1d 403 * 0x07 | | | 404 * 0x11 | | | 405 * 0x2a | | | 406 * 0x34 | | | 407 * 0x35 | | | 408 * 0x36 | | | 409 */ 410 411 int board_eth_init(bd_t *bis) 412 { 413 #ifdef CONFIG_FMAN_ENET 414 struct fsl_pq_mdio_info dtsec_mdio_info; 415 struct tgec_mdio_info tgec_mdio_info; 416 unsigned int i, slot; 417 int lane; 418 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 419 int srds_prtcl = (in_be32(&gur->rcwsr[4]) & 420 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 421 422 printf("Initializing Fman\n"); 423 424 initialize_lane_to_slot(); 425 426 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ 427 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); 428 429 memset(mdio_mux, 0, sizeof(mdio_mux)); 430 431 dtsec_mdio_info.regs = 432 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 433 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 434 435 /* Register the real 1G MDIO bus */ 436 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 437 438 tgec_mdio_info.regs = 439 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 440 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 441 442 /* Register the real 10G MDIO bus */ 443 fm_tgec_mdio_init(bis, &tgec_mdio_info); 444 445 /* Register the three virtual MDIO front-ends */ 446 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 447 "SUPER_HYDRA_RGMII_MDIO"); 448 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 449 "SUPER_HYDRA_FM1_SGMII_MDIO"); 450 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, 451 "SUPER_HYDRA_FM2_SGMII_MDIO"); 452 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, 453 "SUPER_HYDRA_FM1_TGEC_MDIO"); 454 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, 455 "SUPER_HYDRA_FM2_TGEC_MDIO"); 456 457 /* 458 * Program the DTSEC PHY addresses assuming that they are all SGMII. 459 * For any DTSEC that's RGMII, we'll override its PHY address later. 460 * We assume that DTSEC5 is only used for RGMII. 461 */ 462 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 463 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 464 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 465 466 #if (CONFIG_SYS_NUM_FMAN == 2) 467 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 468 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 469 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 470 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 471 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 472 #endif 473 474 switch (srds_prtcl) { 475 case 0: 476 case 3: 477 case 4: 478 case 6: 479 case 0x11: 480 case 0x2a: 481 case 0x34: 482 case 0x36: 483 fm_info_set_phy_address(FM1_DTSEC3, 484 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 485 fm_info_set_phy_address(FM1_DTSEC4, 486 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 487 break; 488 case 1: 489 case 2: 490 case 5: 491 case 7: 492 case 0x35: 493 fm_info_set_phy_address(FM1_DTSEC3, 494 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 495 fm_info_set_phy_address(FM1_DTSEC4, 496 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 497 break; 498 default: 499 printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); 500 break; 501 } 502 503 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 504 int idx = i - FM1_DTSEC1; 505 506 switch (fm_info_get_enet_if(i)) { 507 case PHY_INTERFACE_MODE_SGMII: 508 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 509 if (lane < 0) 510 break; 511 slot = lane_to_slot[lane]; 512 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 513 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 514 idx + 1, slot); 515 switch (slot) { 516 case 1: 517 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 518 BRDCFG1_EMI1_EN; 519 break; 520 case 2: 521 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 522 BRDCFG1_EMI1_EN; 523 break; 524 case 3: 525 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | 526 BRDCFG1_EMI1_EN; 527 break; 528 case 5: 529 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 530 BRDCFG1_EMI1_EN; 531 break; 532 case 6: 533 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 534 BRDCFG1_EMI1_EN; 535 break; 536 case 7: 537 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 538 BRDCFG1_EMI1_EN; 539 break; 540 }; 541 542 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", 543 mdio_mux[i].mask, mdio_mux[i].val); 544 fm_info_set_mdio(i, 545 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); 546 break; 547 case PHY_INTERFACE_MODE_RGMII: 548 /* 549 * FM1 DTSEC5 is routed via EC1 to the first on-board 550 * RGMII port. FM2 DTSEC5 is routed via EC2 to the 551 * second on-board RGMII port. The other DTSECs cannot 552 * be routed to RGMII. 553 */ 554 debug("FM1@DTSEC%u is RGMII at address %u\n", 555 idx + 1, 0); 556 fm_info_set_phy_address(i, 0); 557 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 558 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 559 BRDCFG1_EMI1_EN; 560 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", 561 mdio_mux[i].mask, mdio_mux[i].val); 562 fm_info_set_mdio(i, 563 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); 564 break; 565 case PHY_INTERFACE_MODE_NONE: 566 fm_info_set_phy_address(i, 0); 567 break; 568 default: 569 printf("Fman1: DTSEC%u set to unknown interface %i\n", 570 idx + 1, fm_info_get_enet_if(i)); 571 fm_info_set_phy_address(i, 0); 572 break; 573 } 574 } 575 576 /* 577 * For 10G, we only support one XAUI card per Fman. If present, then we 578 * force its routing and never touch those bits again, which removes the 579 * need for Linux to do any muxing. This works because of the way 580 * BRDCFG1 is defined, but it's a bit hackish. 581 * 582 * The PHY address for the XAUI card depends on which slot it's in. The 583 * macros we use imply that the PHY address is based on which FM, but 584 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 585 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 586 * check the actual slot and just use the macros as-is, even though 587 * the P3041 and P5020 only have one Fman. 588 */ 589 lane = serdes_get_first_lane(XAUI_FM1); 590 if (lane >= 0) { 591 debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); 592 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; 593 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; 594 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", 595 mdio_mux[i].mask, mdio_mux[i].val); 596 } 597 598 fm_info_set_mdio(FM1_10GEC1, 599 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); 600 601 #if (CONFIG_SYS_NUM_FMAN == 2) 602 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 603 int idx = i - FM2_DTSEC1; 604 605 switch (fm_info_get_enet_if(i)) { 606 case PHY_INTERFACE_MODE_SGMII: 607 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 608 if (lane < 0) 609 break; 610 slot = lane_to_slot[lane]; 611 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 612 debug("FM2@DTSEC%u expects SGMII in slot %u\n", 613 idx + 1, slot); 614 switch (slot) { 615 case 1: 616 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | 617 BRDCFG1_EMI1_EN; 618 break; 619 case 2: 620 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | 621 BRDCFG1_EMI1_EN; 622 break; 623 case 3: 624 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | 625 BRDCFG1_EMI1_EN; 626 break; 627 case 5: 628 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | 629 BRDCFG1_EMI1_EN; 630 break; 631 case 6: 632 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | 633 BRDCFG1_EMI1_EN; 634 break; 635 case 7: 636 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | 637 BRDCFG1_EMI1_EN; 638 break; 639 }; 640 641 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", 642 mdio_mux[i].mask, mdio_mux[i].val); 643 fm_info_set_mdio(i, 644 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); 645 break; 646 case PHY_INTERFACE_MODE_RGMII: 647 /* 648 * FM1 DTSEC5 is routed via EC1 to the first on-board 649 * RGMII port. FM2 DTSEC5 is routed via EC2 to the 650 * second on-board RGMII port. The other DTSECs cannot 651 * be routed to RGMII. 652 */ 653 debug("FM2@DTSEC%u is RGMII at address %u\n", 654 idx + 1, 1); 655 fm_info_set_phy_address(i, 1); 656 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; 657 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | 658 BRDCFG1_EMI1_EN; 659 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", 660 mdio_mux[i].mask, mdio_mux[i].val); 661 fm_info_set_mdio(i, 662 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); 663 break; 664 case PHY_INTERFACE_MODE_NONE: 665 fm_info_set_phy_address(i, 0); 666 break; 667 default: 668 printf("Fman2: DTSEC%u set to unknown interface %i\n", 669 idx + 1, fm_info_get_enet_if(i)); 670 fm_info_set_phy_address(i, 0); 671 break; 672 } 673 } 674 675 /* 676 * For 10G, we only support one XAUI card per Fman. If present, then we 677 * force its routing and never touch those bits again, which removes the 678 * need for Linux to do any muxing. This works because of the way 679 * BRDCFG1 is defined, but it's a bit hackish. 680 * 681 * The PHY address for the XAUI card depends on which slot it's in. The 682 * macros we use imply that the PHY address is based on which FM, but 683 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, 684 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we 685 * check the actual slot and just use the macros as-is, even though 686 * the P3041 and P5020 only have one Fman. 687 */ 688 lane = serdes_get_first_lane(XAUI_FM2); 689 if (lane >= 0) { 690 debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); 691 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; 692 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; 693 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", 694 mdio_mux[i].mask, mdio_mux[i].val); 695 } 696 697 fm_info_set_mdio(FM2_10GEC1, 698 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); 699 700 #endif 701 702 cpu_eth_init(bis); 703 #endif 704 705 return pci_eth_init(bis); 706 } 707