1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <command.h>
8 #include <netdev.h>
9 #include <asm/mmu.h>
10 #include <asm/processor.h>
11 #include <asm/cache.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_law.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
18 #include <malloc.h>
19 #include <fm_eth.h>
20 #include <fsl_mdio.h>
21 #include <miiphy.h>
22 #include <phy.h>
23 
24 #include "../common/ngpixis.h"
25 #include "../common/fman.h"
26 #include <fsl_dtsec.h>
27 
28 #define EMI_NONE	0xffffffff
29 #define EMI_MASK	0xf0000000
30 #define EMI1_RGMII	0x0
31 #define EMI1_SLOT3	0x80000000	/* bank1 EFGH */
32 #define EMI1_SLOT4	0x40000000	/* bank2 ABCD */
33 #define EMI1_SLOT5	0xc0000000	/* bank3 ABCD */
34 #define EMI2_SLOT4	0x10000000	/* bank2 ABCD */
35 #define EMI2_SLOT5	0x30000000	/* bank3 ABCD */
36 #define EMI1_MASK	0xc0000000
37 #define EMI2_MASK	0x30000000
38 
39 #define PHY_BASE_ADDR	0x00
40 #define PHY_BASE_ADDR_SLOT5	0x10
41 
42 static int mdio_mux[NUM_FM_PORTS];
43 
44 static char *mdio_names[16] = {
45 	"P4080DS_MDIO0",
46 	"P4080DS_MDIO1",
47 	NULL,
48 	"P4080DS_MDIO3",
49 	"P4080DS_MDIO4",
50 	NULL, NULL, NULL,
51 	"P4080DS_MDIO8",
52 	NULL, NULL, NULL,
53 	"P4080DS_MDIO12",
54 	NULL, NULL, NULL,
55 };
56 
57 /*
58  * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
59  * that the mapping must be determined dynamically, or that the lane maps to
60  * something other than a board slot.
61  */
62 static u8 lane_to_slot[] = {
63 	1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
64 };
65 
66 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
67 {
68 	return mdio_names[(muxval & EMI_MASK) >> 28];
69 }
70 
71 struct mii_dev *mii_dev_for_muxval(u32 muxval)
72 {
73 	struct mii_dev *bus;
74 	char *name = p4080ds_mdio_name_for_muxval(muxval);
75 
76 	if (!name) {
77 		printf("No bus for muxval %x\n", muxval);
78 		return NULL;
79 	}
80 
81 	bus = miiphy_get_dev_by_name(name);
82 
83 	if (!bus) {
84 		printf("No bus by name %s\n", name);
85 		return NULL;
86 	}
87 
88 	return bus;
89 }
90 
91 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
92 int board_phy_config(struct phy_device *phydev)
93 {
94 	if (phydev->drv->config)
95 		phydev->drv->config(phydev);
96 	if (phydev->drv->uid == PHY_UID_TN2020) {
97 		unsigned long timeout = 1 * 1000; /* 1 seconds */
98 		enum srds_prtcl device;
99 
100 		/*
101 		 * Wait for the XAUI to come out of reset.  This is when it
102 		 * starts transmitting alignment signals.
103 		 */
104 		while (--timeout) {
105 			int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
106 			if (reg < 0) {
107 				printf("TN2020: Error reading from PHY at "
108 				       "address %u\n", phydev->addr);
109 				break;
110 			}
111 			/*
112 			 * Note that we've never actually seen
113 			 * MDIO_CTRL1_RESET set to 1.
114 			 */
115 			if ((reg & MDIO_CTRL1_RESET) == 0)
116 				break;
117 			udelay(1000);
118 		}
119 
120 		if (!timeout) {
121 			printf("TN2020: Timeout waiting for PHY at address %u "
122 			       " to reset.\n", phydev->addr);
123 		}
124 
125 		switch (phydev->addr) {
126 		case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
127 			device = XAUI_FM1;
128 			break;
129 		case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
130 			device = XAUI_FM2;
131 			break;
132 		default:
133 			device = NONE;
134 		}
135 
136 		serdes_reset_rx(device);
137 	}
138 
139 	return 0;
140 }
141 #endif
142 
143 struct p4080ds_mdio {
144 	u32 muxval;
145 	struct mii_dev *realbus;
146 };
147 
148 static void p4080ds_mux_mdio(u32 muxval)
149 {
150 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
151 	uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
152 	gpioval |= muxval;
153 
154 	out_be32(&pgpio->gpdat, gpioval);
155 }
156 
157 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
158 				int regnum)
159 {
160 	struct p4080ds_mdio *priv = bus->priv;
161 
162 	p4080ds_mux_mdio(priv->muxval);
163 
164 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
165 }
166 
167 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
168 				int regnum, u16 value)
169 {
170 	struct p4080ds_mdio *priv = bus->priv;
171 
172 	p4080ds_mux_mdio(priv->muxval);
173 
174 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
175 }
176 
177 static int p4080ds_mdio_reset(struct mii_dev *bus)
178 {
179 	struct p4080ds_mdio *priv = bus->priv;
180 
181 	return priv->realbus->reset(priv->realbus);
182 }
183 
184 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
185 {
186 	struct p4080ds_mdio *pmdio;
187 	struct mii_dev *bus = mdio_alloc();
188 
189 	if (!bus) {
190 		printf("Failed to allocate P4080DS MDIO bus\n");
191 		return -1;
192 	}
193 
194 	pmdio = malloc(sizeof(*pmdio));
195 	if (!pmdio) {
196 		printf("Failed to allocate P4080DS private data\n");
197 		free(bus);
198 		return -1;
199 	}
200 
201 	bus->read = p4080ds_mdio_read;
202 	bus->write = p4080ds_mdio_write;
203 	bus->reset = p4080ds_mdio_reset;
204 	sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
205 
206 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
207 
208 	if (!pmdio->realbus) {
209 		printf("No bus with name %s\n", realbusname);
210 		free(bus);
211 		free(pmdio);
212 		return -1;
213 	}
214 
215 	pmdio->muxval = muxval;
216 	bus->priv = pmdio;
217 
218 	return mdio_register(bus);
219 }
220 
221 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
222 				enum fm_port port, int offset)
223 {
224 	if (mdio_mux[port] == EMI1_RGMII)
225 		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
226 
227 	if (mdio_mux[port] == EMI1_SLOT3) {
228 		int idx = port - FM2_DTSEC1 + 5;
229 		char phy[16];
230 
231 		sprintf(phy, "phy%d_slot3", idx);
232 
233 		fdt_set_phy_handle(blob, prop, pa, phy);
234 	}
235 }
236 
237 void fdt_fixup_board_enet(void *fdt)
238 {
239 	int i;
240 
241 	/*
242 	 * P4080DS can be configured in many different ways, supporting a number
243 	 * of combinations of ethernet devices and phy types.  In order to
244 	 * have just one device tree for all of those configurations, we fix up
245 	 * the tree here.  By default, the device tree configures FM1 and FM2
246 	 * for SGMII, and configures XAUI on both 10G interfaces.  So we have
247 	 * a number of different variables to track:
248 	 *
249 	 * 1) Whether the device is configured at all.  Whichever devices are
250 	 *    not enabled should be disabled by setting the "status" property
251 	 *    to "disabled".
252 	 * 2) What the PHY interface is.  If this is an RGMII connection,
253 	 *    we should change the "phy-connection-type" property to
254 	 *    "rgmii"
255 	 * 3) Which PHY is being used.  Because the MDIO buses are muxed,
256 	 *    we need to redirect the "phy-handle" property to point at the
257 	 *    PHY on the right slot/bus.
258 	 */
259 
260 	/* We've got six MDIO nodes that may or may not need to exist */
261 	fdt_status_disabled_by_alias(fdt, "emi1_slot3");
262 	fdt_status_disabled_by_alias(fdt, "emi1_slot4");
263 	fdt_status_disabled_by_alias(fdt, "emi1_slot5");
264 	fdt_status_disabled_by_alias(fdt, "emi2_slot4");
265 	fdt_status_disabled_by_alias(fdt, "emi2_slot5");
266 
267 	for (i = 0; i < NUM_FM_PORTS; i++) {
268 		switch (mdio_mux[i]) {
269 		case EMI1_SLOT3:
270 			fdt_status_okay_by_alias(fdt, "emi1_slot3");
271 			break;
272 		case EMI1_SLOT4:
273 			fdt_status_okay_by_alias(fdt, "emi1_slot4");
274 			break;
275 		case EMI1_SLOT5:
276 			fdt_status_okay_by_alias(fdt, "emi1_slot5");
277 			break;
278 		case EMI2_SLOT4:
279 			fdt_status_okay_by_alias(fdt, "emi2_slot4");
280 			break;
281 		case EMI2_SLOT5:
282 			fdt_status_okay_by_alias(fdt, "emi2_slot5");
283 			break;
284 		}
285 	}
286 }
287 
288 int board_eth_init(bd_t *bis)
289 {
290 #ifdef CONFIG_FMAN_ENET
291 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
292 	int i;
293 	struct fsl_pq_mdio_info dtsec_mdio_info;
294 	struct tgec_mdio_info tgec_mdio_info;
295 	struct mii_dev *bus;
296 
297 	/* Initialize the mdio_mux array so we can recognize empty elements */
298 	for (i = 0; i < NUM_FM_PORTS; i++)
299 		mdio_mux[i] = EMI_NONE;
300 
301 	/* The first 4 GPIOs are outputs to control MDIO bus muxing */
302 	out_be32(&pgpio->gpdir, EMI_MASK);
303 
304 	dtsec_mdio_info.regs =
305 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
306 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
307 
308 	/* Register the 1G MDIO bus */
309 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
310 
311 	tgec_mdio_info.regs =
312 		(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
313 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
314 
315 	/* Register the 10G MDIO bus */
316 	fm_tgec_mdio_init(bis, &tgec_mdio_info);
317 
318 	/* Register the 6 muxing front-ends to the MDIO buses */
319 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
320 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
321 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
322 	p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
323 	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
324 	p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
325 
326 	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
327 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
328 	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
329 	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
330 	fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
331 
332 #if (CONFIG_SYS_NUM_FMAN == 2)
333 	fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
334 	fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
335 	fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
336 	fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
337 	fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
338 #endif
339 
340 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
341 		int idx = i - FM1_DTSEC1, lane, slot;
342 		switch (fm_info_get_enet_if(i)) {
343 		case PHY_INTERFACE_MODE_SGMII:
344 			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
345 			if (lane < 0)
346 				break;
347 			slot = lane_to_slot[lane];
348 			switch (slot) {
349 			case 3:
350 				mdio_mux[i] = EMI1_SLOT3;
351 				fm_info_set_mdio(i,
352 					mii_dev_for_muxval(mdio_mux[i]));
353 				break;
354 			case 4:
355 				mdio_mux[i] = EMI1_SLOT4;
356 				fm_info_set_mdio(i,
357 					mii_dev_for_muxval(mdio_mux[i]));
358 				break;
359 			case 5:
360 				mdio_mux[i] = EMI1_SLOT5;
361 				fm_info_set_mdio(i,
362 					mii_dev_for_muxval(mdio_mux[i]));
363 				break;
364 			};
365 			break;
366 		case PHY_INTERFACE_MODE_RGMII:
367 			fm_info_set_phy_address(i, 0);
368 			mdio_mux[i] = EMI1_RGMII;
369 			fm_info_set_mdio(i,
370 				mii_dev_for_muxval(mdio_mux[i]));
371 			break;
372 		default:
373 			break;
374 		}
375 	}
376 	bus = mii_dev_for_muxval(EMI1_SLOT5);
377 	set_sgmii_phy(bus, FM1_DTSEC1,
378 		      CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
379 
380 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
381 		int idx = i - FM1_10GEC1, lane, slot;
382 		switch (fm_info_get_enet_if(i)) {
383 		case PHY_INTERFACE_MODE_XGMII:
384 			lane = serdes_get_first_lane(XAUI_FM1 + idx);
385 			if (lane < 0)
386 				break;
387 			slot = lane_to_slot[lane];
388 			switch (slot) {
389 			case 4:
390 				mdio_mux[i] = EMI2_SLOT4;
391 				fm_info_set_mdio(i,
392 					mii_dev_for_muxval(mdio_mux[i]));
393 				break;
394 			case 5:
395 				mdio_mux[i] = EMI2_SLOT5;
396 				fm_info_set_mdio(i,
397 					mii_dev_for_muxval(mdio_mux[i]));
398 				break;
399 			};
400 			break;
401 		default:
402 			break;
403 		}
404 	}
405 
406 #if (CONFIG_SYS_NUM_FMAN == 2)
407 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
408 		int idx = i - FM2_DTSEC1, lane, slot;
409 		switch (fm_info_get_enet_if(i)) {
410 		case PHY_INTERFACE_MODE_SGMII:
411 			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
412 			if (lane < 0)
413 				break;
414 			slot = lane_to_slot[lane];
415 			switch (slot) {
416 			case 3:
417 				mdio_mux[i] = EMI1_SLOT3;
418 				fm_info_set_mdio(i,
419 					mii_dev_for_muxval(mdio_mux[i]));
420 				break;
421 			case 4:
422 				mdio_mux[i] = EMI1_SLOT4;
423 				fm_info_set_mdio(i,
424 					mii_dev_for_muxval(mdio_mux[i]));
425 				break;
426 			case 5:
427 				mdio_mux[i] = EMI1_SLOT5;
428 				fm_info_set_mdio(i,
429 					mii_dev_for_muxval(mdio_mux[i]));
430 				break;
431 			};
432 			break;
433 		case PHY_INTERFACE_MODE_RGMII:
434 			fm_info_set_phy_address(i, 0);
435 			mdio_mux[i] = EMI1_RGMII;
436 			fm_info_set_mdio(i,
437 				mii_dev_for_muxval(mdio_mux[i]));
438 			break;
439 		default:
440 			break;
441 		}
442 	}
443 
444 	bus = mii_dev_for_muxval(EMI1_SLOT3);
445 	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
446 	bus = mii_dev_for_muxval(EMI1_SLOT4);
447 	set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
448 
449 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
450 		int idx = i - FM2_10GEC1, lane, slot;
451 		switch (fm_info_get_enet_if(i)) {
452 		case PHY_INTERFACE_MODE_XGMII:
453 			lane = serdes_get_first_lane(XAUI_FM2 + idx);
454 			if (lane < 0)
455 				break;
456 			slot = lane_to_slot[lane];
457 			switch (slot) {
458 			case 4:
459 				mdio_mux[i] = EMI2_SLOT4;
460 				fm_info_set_mdio(i,
461 					mii_dev_for_muxval(mdio_mux[i]));
462 				break;
463 			case 5:
464 				mdio_mux[i] = EMI2_SLOT5;
465 				fm_info_set_mdio(i,
466 					mii_dev_for_muxval(mdio_mux[i]));
467 				break;
468 			};
469 			break;
470 		default:
471 			break;
472 		}
473 	}
474 #endif
475 
476 	cpu_eth_init(bis);
477 #endif /* CONFIG_FMAN_ENET */
478 
479 	return pci_eth_init(bis);
480 }
481